ISEA Project Phase II Sponsored Workshop on Advances in Hardware Security
May 24 - 29, 2019

Latest Updates. || List of External Candidates. || List of Internal Candidates. || Accommodation details (for those requested) will be up soon.
If any more candidates are interested, you may contact course coordinator for seat/accommodation availability.
Program Venue: Seminar Hall, Dept of CSE, IITG. Registration starts at 9 am on 24.05.2019. || [ IIT Guwahati Campus Map]

Shortlisted candidates may plan their travel to Guwahati such that they could reach our campus latest by 23.05.2019, 6 PM. They can plan their return trip anytime after 29.05.2019, 6 PM. Guwahati experiences humid and rainy climate during May with day time temperature going upto 36 degrees. Having an umbrella is desirable while moving through the campus.

Free accommodation for participants from ISEA undertaking institutions is arranged at IITG Campus Guest House in twin sharing rooms.
Self payment basis accommodation for participants from non-ISEA undertaking institutions is arranged at IITG Campus Guest House and hostels as per requests.
Accommodation is from 23.05.19 to 30.05.19.

Download from here Brochure || Application Form DOCX, PDF

About the Workshop

The perspective of the workshop is to generate quality human resource to enhance the research and development in the field of hardware security through a short course consisting of several lectures and interactive discussion sessions, which will cover a wide variety of solutions related to design-for-security as well as SoC security validation techniques (formal verification, side-channel analysis as well as testing methods) to ensure security and trustworthiness of SoCs. The course will touch upon several fundamental questions in this field, mentioned below, and stimulate interest in students and researchers to explore further.

Objective of the Workshop
  • To teach principles of security and trust verification from System-on-Chip (SoC) perspective.

  • To equip students with industry standard skills relating to designing SoCs using third party IPs, and how to verify their security using a combination of formal methods, testing techniques and side-channel analysis.

  • To provide a clear picture of how formal verification techniques (such as model checking, equivalence checking and theorem proving) can be effectively employed for both pre-silicon and post-silicon validation of SoC security and trust.

  • To explore the synergy between logic testing and side channel analysis for detecting hardware Trojans in IoT devices from both pre-silicon and post-silicon perspectives.

  • To understand key challenges of security of IoT devices, interplays between security and other IoT design parameters, such as observability (debug friendliness), power and reliability.

  • To explore and understand security solutions for diverse IoT devices including how industry is approaching in this space. Students will learn the major research topics and the areas, which need major innovations.

  • To understand challenges, and solutions in the hardware security field. It will describe practical experiments and labs to train future engineers and users of IoT devices about the security issues and measures to protect themselves and the nation.

Workshop Contents - Sessionwise Plan
  • Day 1: Friday, May 24 [INTRODUCTION]
  • 9:30 am - 11:00 am: Inaugural Session and Registration
    11:30 am - 1:00 pm: Introduction to Hardware Security Vulnerabilities
    2:45 pm - 4:15 pm: System-on-Chip (SoC) Design using Potentially Untrusted Third-Party IPs
    4:30 pm - 5:00 pm: Q/A
  • Day 2: Saturday, May 25 [DESIGN FOR SECURITY]
  • 9:30 am - 11:00 am: Cryptography and Pseudo-random Number Generator
    11:30 am - 1:00 pm: Logic Locking and Obfuscation
    2:45 pm - 4:15 pm: Watermarking and Physical Unclonable Functions
    4:30 pm - 5:00 pm: Q/A
  • 9:30 am - 11:00 am: Hardware Trojans
    11:30 am - 1:00 pm: Side Channel Attacks
    2:45 pm - 4:15 pm: Exploitation of Test and Debug Structures
    4:30 pm - 5:00 pm: Q/A
  • Day 4: Tuesday, May 28 [SECURITY AND TRUST VALIDATION]
  • 9:30 am - 11:00 am: Simulation-based Security Validation
    11:30 am - 1:00 pm: SoC Security Validation using Side Channel Analysis
    2:45 pm - 4:15 pm: IP Trust Validation using Formal Methods
    4:30 pm - 5:00 pm: Q/A
  • Day 5: Wednesday, May 29 [APPLICATION-SPECIFIC SECURITY]
  • 9:30 am - 11:00 am: Protecting Communication through Network-on-Chip Security
    11:30 am - 1:00 pm: Security of Internet-of-Things and Connected Autonomous Vehicles
    2:45 pm - 4:15 pm: Discussion on collaboration plans, Feedback, Concluding Session
Resource Person

Prof. Prabhat Mishra,
Professor, University of Florida, USA.

Prabhat Mishra is a Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF), where he leads the CISE Embedded Systems Lab. His research interests include embedded and cyber-physical systems, hardware security and trust, energy-aware computing, formal verification, system-on-chip validation, and post-silicon debug. He received his Ph.D. in Computer Science and Engineering from the University of California, Irvine in 2004. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published 7 books, 25 book chapters, and more than 150 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, three Best Paper Awards (ISQED '16, VLSID '11 and CODES+ISSS '03) as well as six Best Paper Nominations (ASPDAC '17, NANOARCH '13, VLSI '13, DATE '12, DAC '09, VLSI '09), and EDAA Outstanding Dissertation Award from the European Design Automation Association. Prof. Mishra currently serves as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems (TODAES), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), and Journal of Electronic Testing (JETTA). He is also serving as an ACM Distinguished Speaker. Prof. Mishra is an ACM Distinguished Scientist and a Senior Member of IEEE.

Eligibility, Registration & Selection

The workshop is open to

  • Faculty from academic and technical institutions.
  • Person from R&D organisations/industries and staff working in R&D projects.
  • Student from CSE/ECE/IT background (B.Tech./M.Sc./MCA/M.Tech./Ph.D.).

Please refer the link of ISEA website for the list of ISEA undertaking organisations. Registration fee is INR 1000 for participants from ISEA undertaking organisations, and INR 2360 (INR 2000 + 18% GST) for participants from non-ISEA undertaking organisations. The registration fee will be refunded to the participants from ISEA undertaking organisations, subject to complete participation in the workshop. There will be a total of 20 seats for the workshop which will be filled based on first come first serve basis.

How To Apply?

1. Take a Demand Draft of the above mentioned amount drawn in favour of Registrar, IIT Guwahati, payable at Guwahati towards registration fee.
2. Download the course Application Form and fill-up (typesetting is preferred over handwritten) all the entries including DD details.
3. Generate a pdf document of the filled up application form and take a printout of the same.
4. Affix your recent passport size color photograph and put your signature in the respective cells.
5. Send the documents and DD via speedpost to the program convener Dr. John Jose (postal address given below) so as to reach IIT Guwahati before the due date.
6. Send a soft copy (preferrably pdf) of the duly filled application form to
7. Fill this Intimation Form after you have sent the application form and the DD via post.

List of selected candidates after Round-I is already displayed on this website. Cosnider this list as formal approval. No separate emails will be sent regarding this.

Registration Fee DD will be returned back (via speed post), if the candidate is not shortlisted.
The registration fee paid will not be refunded to the participants who fail to attend the workshop.

Boarding & Lodging

For participants from ISEA undertaking organisations, accommodation can be arranged free of cost either in the IITG guest house (in twin sharing mode only) or student hostels (single occupancy rooms for gents and double occupancy rooms for ladies) inside IITG campus, based on requests from the applicants. Accommodation is from 23.05.19 to 30.05.19. Registration fee will cover workshop materials and working lunch during the workshop days. Participants can have breakfast and dinner from hostels or guest house on payment basis. Participants from non­-ISEA undertaking organisations should make their own arrangements for boarding and lodging. However, based on requests, accommodation can be arranged in student hostels on a self payment basis subject to availability of seats. No DA/TA will be paid to the participants from ISEA/IIT Guwahati.

IIT Guwahati ISEA Coordinator

Prof. SUKUMAR NANDI, [HomePage]
Department of Computer Science & Engineering,
IIT Guwahati, Guwahati, Assam 781039.
Office: 0361­2582357
Mobile: 9435047835, 9954065267

Program Conveners

Dr. JOHN JOSE, [HomePage]
Assistant Professor,
Department of Computer Science & Engineering,
IIT Guwahati, Guwahati, Assam 781039.
Office: 0361­2583256
Mobile: 9048665842, 9476950747

Assistant Professor,
Department of Computer Science & Engineering,
IIT Guwahati, Guwahati, Assam 781039.
Office: 0361­2582365
Mobile: 8056196455

Accommodation and Registration Support Team

Mrs. Manjari Saha ( || 8133880365),
Mr. Abhijit Das ( || 9774154346),
Mr. Tathagata Barik ( || 8335917973),
PhD Scholars, MARS Research Lab,
Department of Computer Science & Engineering,
IIT Guwahati, Guwahati, Assam 781039.