Assistant Professor
Department of Computer Science & Engineering
Indian Institute of Technology Guwahati
Guwahati - 781039, Assam, India

Contact Details

Office: Room Number H-201, CSE Dept, IITG
Phone: 0361- 2583256
Email: johnjose [AT] iitg [DOT] ac [DOT] in
             johnjose004 [AT] gmail [DOT] com
Home   |   Research   |   Courses   |   Students   |   NPTEL Course   |   External Talks   |   MARS Lab

Upcoming Events      ISEA Workshop on Advances in Hardware Security      ||      TEQIP III Pedagogy Workshop on Effective Teaching

Dr. John Jose works in the broader domain of multicore computer architecture with a special focus to on-chip memory and interconnect optimization techniques of tiled chip multicore processors (TCMP). His research group in Multicore ARchitecture and Systems (MARS) Lab explore problems on enhancing QoS in memory hierarchy, fault tolerant NoC router designs, deflection router designs, wireless NoCs and non-volatile memory techniques. The group also started exploring micro-architectural support in TCMP systems for image and video processing applications by cost effective NoC compression and cache memory prefetching techniques.

Academic Profile
Ph.D Indian Institute of Technology Madras, Chennai, Tamil Nadu 2009-2014
M.Tech Vellore Institute of Technology, Vellore, Tamil Nadu 2004-2006
B.Tech College of Engineering Adoor, Cochin University, Kerala 1999-2003

Professional Experience
Assistant Professor CSE dept, IIT Guwahati, Guwahati July 2015 till date
Assistant Professor Rajagiri School of Engineering & Technology, Cochin July 2013 to June 2015
Visiting Faculty Indian Institute of Information Technology Design and Manufacturing (IIITDM), Chennai January 2013 to April 2013
Teaching & Research Assistant CSE dept, IIT Madras, Chennai January 2009 to June 2013
Lecturer, Assistant Professor Viswajyothi College of Engineering and Technology, Muvattupuzha June 2003 to December 2008
News & Events

SPARC project [Ministry of HRD, Govt of India] titled Approximate Computing Techniques for Resource Constrained Edge Devices with Dr. John Jose as PI and Dr.T.Venkatesh as Co-PI got approved with a budget sanction for 77.48 lakhs. This project is a collaboration work between University of Naples Federico II, Italy, University of Essex, UK, University of Catania, Italy and IIT Guwahati, India.

8 weeks NPTEL course on Advanced Computer Architecture by Dr. John Jose got approved. The course will be online for registration by last week of May 2019.

Sivakumar S, Ph.D scholar from MARS Research Lab received second prize and cash award of INR 30,000 in NXP sponsored design contest event held as part of 32nd IEEE International Conference on VLSI Design [VLSID-2019], held at New Delhi, India, January 2019.

Dipika Deb, Ph.D scholar from MARS Research Lab received the best poster and cash award of INR 20,000 for her work titled Caching Strategy for Prefetch Blocks in TCMPs in Student Research symposium held as part of of 25th IEEE International Conference on High Performance Computing, Data and Analatyics [HiPC-2018], held at Bangalore, India, December 2018.

Abhijit Das, Ph.D scholar from MARS Research Lab received the best Ph.D Forum award for his work titled Optimising NoC in Many-Core Systems at the 26th IFIP/IEEE International Conference on Very Large Scale Integration [VLSI-SoC-2018], held at Verona, Italy on October 8, 2018.