Dr. John Jose works in the domain of multicore computer architecture. His research group in Multicore ARchitecture and Systems (MARS) Lab explore problems in the following domain. For more details about ongoing research click here.
- Network on Chip (NoC) and Cache Optimisation in Tiled Chip Multi-Processors (TCMP)
- Wireless On Chip Interconnects and Edge/Fog Computing
- Machine Learning based accelerators for NoCs
- Non-Volatile Memory (NVM) Technology
- Secure System on Chip Design Techniques
- Disaggregated Memory Management in Data Center Architectures
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Academic Profile
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Professional Experience
| Assistant Professor, CSE Department, IIT Guwahati, Guwahati. |
2015 till date |
| Assistant Professor, Rajagiri School of Engineering & Technology, Cochin. |
2013 to 2015 |
| Visiting Faculty, Indian Institute of Information Technology Design and Manufacturing (IIITDM), Kancheepuram. |
2013 (6 months) |
| Teaching & Research Assistant, CSE Department, IIT Madras, Chennai. |
2009 to 2013 |
| Lecturer, Assistant Professor, Viswajyothi College of Engineering and Technology, Muvattupuzha. |
2003 to 2008 |
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News Highlights 
Oct 10, 2020: IITG organizes ISEA-Virtual Presentation Conclave [IVPC-2020]. Submission deadline - 05.11.2020.
Oct 05, 2020: Paper titled COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC based MPSoCs by Dipika Deb et al. is accepted for publication in ACM Transactions on Design Automation of Electronic Systems [ACM-TODAES].
Sept 22, 2020: Abhishek Kumar received the best thesis award from M.Tech-CSE (2019-20 batch) in the 22nd Convocation of IITG for the thesis titled Exploiting NoC Buffers as Victim Cache between Last Level Cache and Main Memory.
Aug 16, 2020: Paper titled Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors by Joe Augustine et al. is accepted as a full paper at 38th IEEE International Conference on Computer Design [ICCD-2020] to be held in October 2020 (Virtual event).
Aug 16, 2020: Paper titled Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers by Abhijit Das et al. is accepted as a full paper at 38th IEEE International Conference on Computer Design [ICCD-2020] to be held in October 2020 (Virtual event).
Last updated on 30.10.2020.
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