JOHN JOSE

Assistant Professor
Department of Computer Science & Engineering
Indian Institute of Technology Guwahati
Guwahati - 781039, Assam, India

Contact Details

Office: Room Number H-201, CSE Dept, IITG
Phone: 0361- 2583256
Email: johnjose [AT] iitg [DOT] ac [DOT] in
             johnjose004 [AT] gmail [DOT] com
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Dr. John Jose works in the broader domain of multicore computer architecture with a special focus to on-chip memory and interconnect optimization techniques of tiled chip multicore processors (TCMP). His research group in Multicore ARchitecture and Systems (MARS) Lab explore problems on enhancing QoS in memory hierarchy, fault tolerant NoC router designs, deflection router designs, wireless NoCs and non-volatile memory techniques. The group also started exploring micro-architectural support in TCMP systems for image and video processing applications by cost effective NoC compression and cache memory prefetching techniques.

Academic Profile
Ph.D Indian Institute of Technology Madras, Chennai, Tamil Nadu 2009-2014
M.Tech Vellore Institute of Technology, Vellore, Tamil Nadu 2004-2006
B.Tech College of Engineering Adoor, Cochin University, Kerala 1999-2003

Professional Experience
Assistant Professor, CSE Department, IIT Guwahati, Guwahati. July 2015 till date
Assistant Professor, Rajagiri School of Engineering & Technology, Cochin. July 2013 to June 2015
Visiting Faculty, Indian Institute of Information Technology Design and Manufacturing (IIITDM), Kancheepuram. January 2013 to April 2013
Teaching & Research Assistant, CSE Department, IIT Madras, Chennai. January 2009 to June 2013
Lecturer, Assistant Professor, Viswajyothi College of Engineering and Technology, Muvattupuzha. June 2003 to December 2008
News & Events

Dr. John Jose is invited to serve as Co-Chair for Digital Design & Architecture track of International Conference on VLSI Design [VLSID-2020] to be held at Bengaluru, January 2020.

Dr. John Jose is invited to lead a one week FDP on Advances in Multicore Computer Architecture Design at National Institute of Engineering, Mysore [08.07.2019 to 12.07.2019].

Paper titled ECAP:Energy Efficient CAching for Prefetch Blocks in Tiled Chip MultiProcessors by D. Dipika et al. is accepted for publication in IET-Computers and Digital Techniques journal.

Registration started for 8 weeks NPTEL Online Certification Course on Advanced Computer Architecture by Dr. John Jose.

Dr. Amit Kumar Singh , University of Essex, UK is visiting IITG as SPARC project resource person in August 2019.

SPARC project [Ministry of HRD, Govt of India] titled Approximate Computing Techniques for Resource Constrained Edge Devices with Dr. John Jose as PI and Dr.T.Venkatesh as Co-PI is approved with a budget sanction for 77.48 lakhs.