Chandan Karfa

Assistant Professor, Department of CSE
IIT Guwahati, Guwahati - 781039
Assam, India

Room No.: H-002
Phone: +91 361 2582375
Email: ckarfa @ iitg.ac.in

Personal Webpage: Click here to visit.


Education

PhD
Formal Verification of Behavioural Transformations, Department of Computer Science and Engineering, IIT Kharagpur, 2011.

MS (by Research)
Formal Verification of High-level Synthesis, Department of Computer Science and Engineering, IIT Kharagpur, 2007.

B.Tech (IT)
Information Technology, University of Kalyani, West Bangal, 2004.


Work Experiences

Visiting Researcher
New York University, May 2019 - July 2019.

Senior R&D Engineer
Synopsys (India) Pvt. Ltd, September 2011 - July 2016.


Research Interests

Formal Verification, High-level Synthesis, Electronic Design Automation, Hardware Security, Verification of Compiler Optimizations.


Primary Research Group

Computer Architecture and Embedded Systems

Courses Offered

  • 2016-2017 ⋄ Even Semester ⋄ CS201 : Discrete Mathematics
  • 2016-2017 ⋄ Even Semester ⋄ CS210 : Data Structure Laboratory

Ph.D. Students continuing

  • PRIYANKA PANIGRAHI
  • DEBABRATA SENAPATI
  • Adem Mohammed Abderehman
  • Cherinet Kejela Addise
  • Sanjit Kumar Roy

M.Tech. Students Completed

  • Supervisor: Chandan Karfa ⋄ Scholar Name: PANKAJ KUMAR KALITA ⋄ Thesis Title: "Inverse Operation Detection and Counter Example Generation during Path Based Equivalence Checking"

Sponsored Research Projects

Project Title: "Security Analysis of Compiler Optimization Techniques "
PI: Prof.Chandan Karfa
Funding Agency: CRG, Department of Science & Technology (DST), Govt. of India.
Start Year: 2020
End Year: 2022

Project Title: "Institute Start-up Research Grant -- top up grant"
PI: Chandan Karfa
Funding Agency: IIT Guwhati
Start Year: 2018
End Year: 2018

Project Title: "Formal Verification of Optimizing Transformations of Programs and Optimizations for FPGAs "
PI: Prof.Chandan Karfa
Funding Agency: Institute Start-up Research Grant
Start Year: 2017
End Year: 2018

Project Title: "Formal Verification of Optimizing Transformations of Programs and Optimizations for FPGAs "
PI: Prof.Chandan Karfa
Funding Agency: ECR, Department of Science and Technology (DST), Govt. of India.
Start Year: 2017
End Year: 2020

Publications

  • R. Chuksey, C. Karfa, "Verification of Scheduling of Conditional Behaviors in High-level Synthesis", "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", 8, 1638-1651, July, 2020

  • Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg and Ramesh Karri, "Is Register Transfer Level Locking Secure Against SAT Attacks?", Design, Automation and Test in Europe Conference & Exhibition (DATE), 550-555, March, 2020

  • Surajit Das, Chandan Karfa, Santosh Biswas, "Formal Modeling of Network-on-Chip Using CFSM and Its Application in Detecting Deadlock", "IEEE Transactions on Very Large Scale Integration (VLSI) Systems", 28, 1016 - 1029, January, 2020

  • C. Karfa, D. Sarkar, C. Mandal, "Verification of parallelising transformations of KPN models", "IET Cyber-Physical Systems: Theory & Applications", 4, 276 - 289, October, 2019

  • R. Chouksey, C. Karfa, K. Banerjee, P. K. Kalita and P. Bhaduri, "Counter-example generation procedure for path-based equivalence checkers", "IET Software", 13, 280-285, August, Link, 2019

  • Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, "Formal Verification of Optimizing Transformations during High-level Synthesis", ISEC 2019, 27:1-27:5, February, Link, 2019

  • Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri , "Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples", 32nd International Conference on VLSI Design 2019, 377-382, January, Link, 2019

  • Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, "Translation Validation of Code Motion Transformations Involving Loops", "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", June, Link, 2018

  • R. Chouksey, C. Karfa and P. Bhaduri, "Translation Validation of Loop Invariant Code Optimizations Involving False Computations", 21st International Symposium on VLSI Design and Test (VDAT 2017), 767-778, July, Link, 2017

  • C. Karfa, "Replication Strategies for FPGAs", Synopsys India Technical Conference 2016, 2016

  • C. Karfa, "Automatic Register Balancing in Model-based High-level Synthesis", 6th Asia Symposium on Quality Electronic Design (ASQED 2015), 43-49, 2015

  • K. Banerjee, C. Karfa, D. Sarkar, C Mandal, "Verification of Code Motion Techniques using Value Propagation", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 33, 1180-1193, 2014

  • C. Karfa, S. Jain, "On Multi-cycle Path Support in Model based High-level Synthesis", IEEE Students Technology Symposium 2014, 253-258, 2014

  • C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Verification of loop and arithmetic transformations of array-intensive behaviors", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 32, 1787-1800, 2013

  • C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Experimentation with SMT Solvers and Theorem Provers for Verification of Loop and Arithmetic Transformations", 5th IBM Collaborative Academia Research Exchange (I-CARE 2013), 3:1-3:4, 2013

  • C. Karfa, D. Sarkar, C Mandal, "Verification of KPN level transformation", 26th International Conference on VLSI Design (VLSID) 2013, 338-343, 2013

  • C. Karfa, D. Sarkar, C Mandal, "Formal Verification of Code Motion Techniques using Data-flow Driven Equivalence Checking", "ACM Transactions on Design Automation of Electronic Systems", 17, 30:1--30:37, 2012

  • C. Karfa, "Application of Behavioural Transformations in Embedded System Design", "IETE Technical Review", 29, 372-379, 2012

  • C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques", IEEE International Symposium on Electronic System Design (ISED) 2012, 67-71, 2012

  • C. Karfa, D. Sarkar, C Mandal, "Verification of Register Transfer Level Low Power Transformations", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, 313-314, 2011

  • C. Karfa, D. Sarkar, C Mandal, "Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 29, 479-492, 2010

  • C. Karfa, D. Sarkar, C Mandal, "Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2010, 428-433, 2010

  • C. Karfa, D. Sarkar, C Mandal, P. Kumar, "An Equivalence Checking Method for Scheduling Verification in High-level Synthesis", "IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems", 27, 556-569, 2008

  • C. Karfa, D. Sarkar, C Mandal, "Verification of Data-path and Controller Generation Phase in High-level Synthesis", 15th IEEE International Conference on Advanced Computing and Communication (ADCOM 2007), 315-320, 2007

  • C. Karfa, D. Sarkar and C Mandal, "Hand-in-hand Verification of High-level Synthesis", ACM Great Lakes Symposium on VLSI 2007, 429-434, 2007

  • C. Karfa, C. Mandal, D. Sarkar, C. Reade, "Register Sharing Verification during Data-path Synthesis", IEEE International Conference on Computing: Theory and Application 2007, 135-140, 2007

  • S. Biswas, C. Karfa, H. Kanwar, D.Sarkar, S. Mukhopadhyay A. Patra, "Fairness of Transitions in Diagnosability Analysis of Hybrid Systems", American Control Conference, 2006, 2664-2669, July, 2006

  • C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade, "A Formal Verification Method of Scheduling in High-level Synthesis", IEEE International Symposium on Quality Electronic Design 2006, 71-76, 2006

  • C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade, "Verification of Scheduling in High-level Synthesis", IEEE Computer Society Annual Symposium on VLSI 2006, 141-146, 2006

  • C. Karfa, J. S. Reddy, S. Biswas, C. R. Mandal, D. Sarkar, "SAST An Interconnection aware high level synthesis tool", VLSI Design and Test (VDAT 2005), 285-293, 2005

  • C. Karfa, K. Banerjee, D. Sarkar, C Mandal, "Equivalence Checking of Array-Intensive Programs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, 156-161

Recognitions

  • TechInventor Award 2013, India Electronics and Semiconductor Association (IESA)

  • Innovative Student Projects Award 2013 (Doctoral Level), Indian National Academy of Engineering (INAE)

  • Best Paper Award, 5th IBM Collaborative Academia Research Exchange 2013

  • 2nd Runner-up TechVista 2010, Microsoft Research India annual research symposium

  • Winner of EDA software contest, 22nd international conference on VLSI design and embedded systems 2009

  • Microsoft Research India PhD Fellowship 2008-2012, Microsoft Research India

  • Innovative Student Projects Award 2008 (Master Level), Indian National Academy of Engineering (INAE)

  • Best Paper Award, ADCOM 2007