MHRD Sponsored GIAN Course on Scalable On-Chip Interconnects for Many-Core Systems
Indian Institute of Technology Guwahati, May 24 - 30, 2017.

Brochure  |   Overview & Objectives  |   Resource Persons  |   Course Details  |   Accomodation  |   Contact

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Venue of the Course: NKN-Virtual Class Room, 2nd Floor, Core-3, Academic Complex, IIT Guwahati

Participant's group photo and certificate distribution photos Click here

For Simulator Setup and Guidelines Click Here.

Marks/grades of the course exam is available Here.

How to reach IIT Guwahati Campus ? The institute is located on the outskirts of the city of Guwahati (on the north side of Brahmaputra river) at a distance of around 20 km from Guwahati railway station and around 22 km from the Lokapriya Gopinath Bordoloi airport. Pre-paid taxi service is avaialable at airport, which cost approximately Rs.550 from airport to IIT Guwahati. Radio taxi services from Prime Cab (0361-222-2233), My Taxi (0361-222-8888) are also available from the airport to IIT Guwahati. If you prefer a radio cab, it is advisable to reserve a cab by giving your mobile number before (minimum 30 minutes) to your arrival in Guwahati. Smart phone app based cab services from ola, uber etc are available from airport and railway station (approximate price Rs.300/-).
Taxis, buses and auto-rickshaws are available to reach the IIT Guwahati campus from the railway station and other parts of the city. IIT Guwahati also has its own bus service (labelled an Green Valley) that operates once in a hour between Guwahati city (from near Reserve Bank of India, Guwahati Office near to paltform-1 of Guwahati railway station) and the IITG campus. Bus timings are here. (Starting point is shown as PB in the bus schedule chart.)

Course Overview & Objectives

Power and thermal constraints has led the processor industry to embrace multicore architectures. In continuation with the evolution of processor technology, researchers have started focusing on many core processor designs with more than 100 cores on a single chip. This paradigm shift towards many core designs has resulted in a renewed interest in on-chip interconnect design due to the complexity and criticality involved in the communication pattern of such massively parallel systems. On-chip interconnects play a major role in shaping the power and performance profiles of multicore processors. As a scalable substitute for time shared on-chip bus, Network-on-Chip (NoC) is proposed as the communication infrastructure in modern multi/many-core System-on-Chips (SoC). Efficient communication in NoC is critical to the overall SoC performance.

This GIAN course is basically organized into 4 modules: - (1) Introduction to NoC architectures, (2) Performance improvement in NoC by adaptive routing and throttling, (3) Energy efficient NoC designs, (4) Emerging NoC architectures.

The course contains (a) regular lecture sessions (b) hands on sessions on open source full system architectural simulator-GEM5, together with interconnect model GARNET (c) problem solving & tutorial sessions for deeper understanding of advanced concepts. The course also provides an opportunity to the participants who are interested in the field of computer architecture in general and on-chip interconnection sys-tems in particular to have fruitful association/ collaboration with Multicore Architecture and Systems (MARS) Research Group of CSE department, IIT Guwahati in terms of collaborative research, student project co-mentoring and internships. The course will also throws light on few emerging research problems in NoC domain upon which the participants can work on, once they go back to their parent institutions with necessary support from the course coordinator.

Resource Persons

Foreign Faculty

Host Faculty

Dr. Maurizio Palesi,
Associate Professor,
University of Catania, Italy.

Dr. John Jose,
Assistant Professor,
IIT Guwahati, India.

Course Details

Who can attend?
  • Faculty from academic and technical institutions.
  • Persons from R&D organizations/ industries and staff working in R& D projects.
  • Student from CSE/ECE/IT background (B.Tech/MSc/MCA/M.Tech/Ph.D).
Course Fee Structure
  • Participants from abroad : US$ 500
  • Industry/ Research Organizations : INR 8000
  • Faculty from Academic Institutions: INR 4000
  • Indian students : INR 1000 (*Refundable after course completion).
  • The above fee includes all instructional materials, computer use for lab/ tutorial sessions and internet facility.
Registration Procedure
  • Go to GIAN website and register. You need to pay a one-time fee of INR 500/- for portal registration.
  • Select the course - 161006D01: Scalable On-chip Interconnects for Many-Core Systems. Save and confirm the course.
  • Once you enroll for the course, the course coordinator will be notified.
  • The course coordinator will shortlist the candidates, and selected candidates will be notified by email.
  • The selected candidates must pay the applicable fees by a DD (details of the DD will be mentioned in the selection mail).
  • Send the print out of the course registration form and the DD to the course coordinator within stipulated time mentioned in the selection mail.
  • Please keep the copy of the registration form and DD for future reference and correspondence.


For academic faculty & industry personnel
  • Accommodation can be arranged on IITG guest house on a self payment basis of Rs. 275/night/person.
  • Rooms will be allotted on twin sharing basis (other person will also be a participant of this GIAN course).
  • Accomodation is arranged from May 23 to May 31, 2017.
  • Breakfast, lunch and dinner can be taken from campus guest house (Breakfast Rs. 63/-, Lunch Rs. 126/- and Dinner Rs. 126/-).
  • They can also dine from student hostel messes (Breakfast Rs. 30/-, Lunch Rs. 45/- and Dinner Rs. 45/-) or from other canteens/ restaurants available in the campus.
For students
  • Accommodation can be arranged on student hostels (Siang hostel for boys and Subansiri hostel for girls) on a self payment basis of Rs. 150/night/person.
  • Rooms will be allotted on twin sharing basis in girls hostel and independenet rooms in boys hostel.
  • Accomodation is arranged from May 23 to May 31, 2017.
  • Breakfast, lunch and dinner can be taken from the respective hostel messes by paying a nominal charge. (Breakfast Rs. 30/-,Lunch Rs. 45/- and Dinner Rs. 45/-)
  • They can also dine from other canteens and restaurants available in the campus.
Amount for food can be paid as and when you dine in the respective messes/ canteens.
Pre-Booking of accomodation is closed.


Dr. John Jose (Course Co-ordinator),
Assistant Professor, Department of Computer Science and Engineering,
Indian Institute of Technology Guwahati, North Guwahati, Assam, Pin 781039.
Email: johnjose [AT] iitg [DOT] ernet [DOT] in
Telephone: Office- (0361) 258-3256 , Mobile:+91-9048665842 or +91-9476850747

Mr. Abhijit Das : Ph.D Scholar, CSE dept (Volunteer in charge of registration & logistics): +91-9774154346 / +91-7002790319
Mr. Sibarpit Chandan : M.Tech Student, CSE dept (Volunteer in charge of Siang hostel accomodation): +91-9435686604
Ms. Manjari Saha : Ph.D Scholar, CSE dept ((Volunteer in charge of Subansiri hostel accomodation): +91-8133880365
Reception, IIT Guwahati Guest house: (0361)-2582900