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Chandan Karfa

Publications

Journals

  1. Debabrata Senapati, Kaushik Rajesh, Arnab Sarkar and Chandan Karfa, “TMDS: A Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems,” ACM Transactions on Design Automation of Electronic Systems, pp. 1-22, 2023.
    [BibTeX] 

    
@article{DebabrataTODAES23,

  author = {Senapati, Debabrata and Rajesh, Kaushik and Sarkar, Arnab and Karfa, Chandan},

  title = {TMDS: A Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems},

  journal = {ACM Transactions on Design Automation of Electronic Systems},

  year = {2023},

  pages = {1-22},

  doi = {https://doi.org/10.1145/3616869}

}

  2. Priyanka Panigrahi and Chandan Karfa, “Translation Validation of Information Leakage of Compiler Optimizations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-14, 2023.
    [BibTeX] 

    
@article{PriyankaTCAD23,

  author = {Panigrahi, Priyanka and Karfa, Chandan},

  title = {Translation Validation of Information Leakage of Compiler Optimizations},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2023},

  pages = {1-14},

  doi = {https://doi.org/10.1109/TCAD.2023.3269954}

}

  3. Surajit Das, Chandan Karfa and Santosh Biswas, “Accelerating NoC Verification Using a Complete Model and Active Window,” IEEE Access, vol. 10, pp. 88985-88999, 2022.
    [BibTeX] 

    
@article{SurajitAccess,

  author = {Das, Surajit and Karfa, Chandan and Biswas, Santosh},

  title = {Accelerating NoC Verification Using a Complete Model and Active Window},

  journal = {IEEE Access},

  year = {2022},

  volume = {10},

  pages = {88985-88999},

  doi = {https://doi.org/10.1109/ACCESS.2022.3199671}

}

  4. Surajit Das and Chandan Karfa, “Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC,” IEEE Embedded Systems Letters, vol. 14, no. 2, pp. 67-70, 2022.
    [BibTeX] 

    
@article{9540770,

  author = {Das, Surajit and Karfa, Chandan},

  title = {Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC},

  journal = {IEEE Embedded Systems Letters},

  year = {2022},

  volume = {14},

  number = {2},

  pages = {67-70},

  doi = {https://doi.org/10.1109/LES.2021.3113355}

}

  5. Mohammed Abderehman, Rupak Gupta, Rakesh Reddy Theegala and Chandan Karfa, “BLAST: Belling the Black-Hat High-Level Synthesis Tool,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 3661-3672, 2022.
    [BibTeX] 

    
@article{MohammedTCAD22,

  author = {Abderehman, Mohammed and Gupta, Rupak and Theegala, Rakesh Reddy and Karfa, Chandan},

  title = {BLAST: Belling the Black-Hat High-Level Synthesis Tool},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2022},

  volume = {41},

  number = {11},

  pages = {3661-3672},

  doi = {https://doi.org/10.1109/TCAD.2022.3200513}

}

  6. Debabrata Senapati, Arnab Sarkar and Chandan Karfa, “Energy-aware Real-time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2022.
    [BibTeX] 

    
@article{DebabrataTCAD22,

  author = {Senapati, Debabrata and Sarkar, Arnab and Karfa, Chandan},

  title = {Energy-aware Real-time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2022},

  pages = {1-1},

  doi = {https://doi.org/10.1109/TCAD.2022.3228504}

}

  7. Debabrata Senapati, Arnab Sarkar and Chandan Karfa, “PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms,” IEEE Transactions on Computers, vol. 71, no. 2, pp. 421-435, 2022.
    [BibTeX] 

    
@article{9326385,

  author = {Senapati, Debabrata and Sarkar, Arnab and Karfa, Chandan},

  title = {PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms},

  journal = {IEEE Transactions on Computers},

  year = {2022},

  volume = {71},

  number = {2},

  pages = {421-435},

  doi = {https://doi.org/10.1109/TC.2021.3052389}

}

  8. Priyanka Panigrahi, Abhik Paul and Chandan Karfa, “Quantifying Information Leakage for Security Verification of Compiler Optimizations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4385-4396, 2022.
    [BibTeX] 

    
@article{PriyankaTCAD22,

  author = {Panigrahi, Priyanka and Paul, Abhik and Karfa, Chandan},

  title = {Quantifying Information Leakage for Security Verification of Compiler Optimizations},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2022},

  volume = {41},

  number = {11},

  pages = {4385-4396},

  doi = {https://doi.org/10.1109/TCAD.2022.3200914}

}

  9. Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa and Prabhat Mishra, “Secure Register Allocation for Trusted Code Generation,” IEEE Embedded Systems Letters, vol. 14, no. 3, pp. 127-130, 2022.
    [BibTeX] 

    
@article{PriyankaESL,

  author = {Panigrahi, Priyanka and Sahithya, Vemuri and Karfa, Chandan and Mishra, Prabhat},

  title = {Secure Register Allocation for Trusted Code Generation},

  journal = {IEEE Embedded Systems Letters},

  year = {2022},

  volume = {14},

  number = {3},

  pages = {127-130},

  doi = {https://doi.org/10.1109/LES.2022.3151096}

}

  10. M. Abderrahman, J. Patidar, J. Oza, Y. Nigam, T. M. AbdulKhader and C. Karfa, “FastSim: A Fast Simulation Framework for High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1371-1385, May 2022.
    [BibTeX] 

    
@article{FastSimTCAD,

  author = {M. Abderrahman and J. Patidar and J. Oza and Y. Nigam and TM AbdulKhader and C. Karfa},

  title = {FastSim: A Fast Simulation Framework for High-Level Synthesis},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2022},

  volume = {41},

  number = {5},

  pages = {1371-1385}

}

  11. Debabrata Senapati, Arnab Sarkar and Chandan Karfa, “HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems,” ACM Trans. Embed. Comput. Syst., vol. 20, no. 5s, sep 2021.
    [BibTeX] [URL] 

    
@article{10.1145/3477037,

  author = {Senapati, Debabrata and Sarkar, Arnab and Karfa, Chandan},

  title = {HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems},

  journal = {ACM Trans. Embed. Comput. Syst.},

  publisher = {Association for Computing Machinery},

  year = {2021},

  volume = {20},

  number = {5s},

  url = {https://doi.org/10.1145/3477037},

  doi = {https://doi.org/10.1145/3477037}

}

  12. R. Chouksey and C. Karfa, “Verification of Scheduling of Conditional Behaviors in High-level Synthesis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 7, pp. 1638-1651, July 2020.
    [BibTeX] 

    
@article{ramanujTVLSI20,

  author = {R. Chouksey and C. Karfa},

  title = {Verification of Scheduling of Conditional Behaviors in High-level Synthesis},

  journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},

  year = {2020},

  volume = {28},

  number = {7},

  pages = {1638-1651}

}

  13. S. Das, C. Karfa and S. Biswas, “Formal Modeling of Network-on-Chip Using CFSM and Its Application in Detecting Deadlock,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 4, pp. 1016-1029, April 2020.
    [BibTeX] 

    
@article{surajitTVLSI20,

  author = {S. Das and C. Karfa and S. Biswas},

  title = {Formal Modeling of Network-on-Chip Using CFSM and Its Application in Detecting Deadlock},

  journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},

  year = {2020},

  volume = {28},

  number = {4},

  pages = {1016-1029},

  doi = {https://doi.org/10.1109/TVLSI.2019.2959618}

}

  14. S. Maddheshiya, R. Chouksey and C. Karfa, “VP_TT: A Value Propagation Based Equivalence Checker for Testability Transformations,” IET Software, vol. 15, no. 1, pp. 147-159, February 2020.
    [BibTeX] 

    
@article{Maddheshiya2020,

  author = {S. Maddheshiya and R. Chouksey and C. Karfa},

  title = {VP_TT: A Value Propagation Based Equivalence Checker for Testability Transformations},

  journal = {IET Software},

  year = {2020},

  volume = {15},

  number = {1},

  pages = {147-159}

}

  15. Chandan Karfa, Chittaranjan Mandal and Dipankar Sarkar, “Verification of parallelising transformations of KPN models,” IET Cyber-Physical Systems: Theory & Applications, vol. 4, no. 3, pp. 276-289, September 2019.
    [BibTeX] 

    
@article{karfa2019-kpn,

  author = {Chandan Karfa and Chittaranjan Mandal and Dipankar Sarkar},

  title = {Verification of parallelising transformations of KPN models},

  journal = {IET Cyber-Physical Systems: Theory & Applications},

  year = {2019},

  volume = {4},

  number = {3},

  pages = {276-289}

}

  16. R. Chouksey, C. Karfa, K. Banerjee, P. K. Kalita and P. Bhaduri, “Counter-example generation procedure for path-based equivalence checkers,” IET Software, vol. 13, no. 4, pp. 280-285, August 2019.
    [BibTeX] 

    
@article{Chouksey2019,

  author = {R. Chouksey and C. Karfa and K. Banerjee and P. K. Kalita and P. Bhaduri},

  title = {Counter-example generation procedure for path-based equivalence checkers},

  journal = {IET Software},

  year = {2019},

  volume = {13},

  number = {4},

  pages = {280-285},

  doi = {https://doi.org/10.1049/iet-sen.2018.5203}

}

  17. R. Chouksey, C. Karfa and P. Bhaduri, “Translation Validation of Code Motion Transformations Involving Loops,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 7, pp. 1378-1382, July 2019.
    [BibTeX] 

    
@article{ramanujtcad,

  author = {R. Chouksey and C. Karfa and P. Bhaduri},

  title = {Translation Validation of Code Motion Transformations Involving Loops},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  year = {2019},

  volume = {38},

  number = {7},

  pages = {1378-1382}

}

  18. Kunal Banerjee, Chandan Karfa, Dipankar Sarkar and Chittaranjan A. Mandal, “Verification of Code Motion Techniques Using Value Propagation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 8, pp. 1180-1193, Aug 2014.
    [BibTeX] 

    
@article{karfa2014valuepropagation,

  author = {Kunal Banerjee and Chandan Karfa and Dipankar Sarkar and Chittaranjan A. Mandal},

  title = {Verification of Code Motion Techniques Using Value Propagation},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  publisher = {IEEE},

  year = {2014},

  volume = {33},

  number = {8},

  pages = {1180--1193}

}

  19. Chandan Karfa, Kunal Banerjee, Dipankar Sarkar and Chittaranjan A. Mandal, “Verification of loop and arithmetic transformations of array-intensive behaviors,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 32, no. 11, pp. 1787-1800, Oct 2013.
    [BibTeX] 

    
@article{karfa2013array-intensive,

  author = {Chandan Karfa and Kunal Banerjee and Dipankar Sarkar and Chittaranjan A. Mandal},

  title = {Verification of loop and arithmetic transformations of array-intensive behaviors},

  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},

  publisher = {IEEE},

  year = {2013},

  volume = {32},

  number = {11},

  pages = {1787--1800}

}

  20. Chandan Karfa, “Application of Behavioural Transformations in Embedded System Design,” IETE Technical Review, vol. 29, no. 5, pp. 372-379, 2012.
    [BibTeX] 

    
@article{karfa2012IETE,

  author = {Chandan Karfa},

  title = {Application of Behavioural Transformations in Embedded System Design},

  journal = {IETE Technical Review},

  publisher = {IETE},

  year = {2012},

  volume = {29},

  number = {5},

  pages = {372-379}

}

  21. Chandan Karfa, Chittaranjan A. Mandal and Dipankar Sarkar, “Formal verification of code motion techniques using data-flow-driven equivalence checking,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 17, no. 3, pp. 30:1-30:37, Jul 2012.
    [BibTeX] 

    
@article{karfa2012data-flow,

  author = {Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar},

  title = {Formal verification of code motion techniques using data-flow-driven equivalence checking},

  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},

  publisher = {ACM},

  year = {2012},

  volume = {17},

  number = {3},

  pages = {30:1--30:37}

}

  22. Chandan Karfa, Dipankar Sarkar and Chitta Mandal, “Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits,” IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 29, no. 3, pp. 479-492, Feb 2010.
    [BibTeX] 

    
@article{karfa2010high-level,

  author = {Chandan Karfa and Dipankar Sarkar and Chitta Mandal},

  title = {Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits},

  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},

  publisher = {IEEE},

  year = {2010},

  volume = {29},

  number = {3},

  pages = {479--492}

}

  23. Chandan Karfa, Dipankar Sarkar, Chitta Mandal and P. Kumar, “An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 556-569, Mar 2008.
    [BibTeX] 

    
@article{karfa2008equivalence-checking,

  author = {Chandan Karfa and Dipankar Sarkar and Chitta Mandal and P. Kumar},

  title = {An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis},

  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

  publisher = {IEEE},

  year = {2008},

  volume = {27},

  number = {3},

  pages = {556--569}

}

Conferences

  1. Debabrata Senapati, Arnab Sarkar Dharmendra Maurya and Chandan Karfa, “ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems,” in 37th International Conference of VLSI Design (VLSID 2024), 2024.
    [BibTeX] 

    
@inproceedings{DebabrataVLSID24,

  author = {Debabrata Senapati and Dharmendra Maurya, Arnab Sarkar and Chandan Karfa},

  title = {ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems},

  booktitle = {37th International Conference of VLSI Design (VLSID 2024)},

  year = {2024}

}

  2. Praveen Karmakar, Marpina Bharani and Chandan Karfa, “Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction,” in 37th International Conference of VLSI Design (VLSID 2024), 2024.
    [BibTeX] 

    
@inproceedings{PraveenVLSID24,

  author = {Praveen Karmakar and Marpina Bharani and Chandan Karfa},

  title = {Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction},

  booktitle = {37th International Conference of VLSI Design (VLSID 2024)},

  year = {2024}

}

  3. Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Peddaiahgari Reddy, Disha Puri, Anshul Jain, Arijit Sur and Pradip Prajapati, “RTL Simulation Acceleration with Machine Learning Models,” in 25th International Symposium on Quality Electronic Design (ISQED'24), 2024.
    [BibTeX] 

    
@inproceedings{SurajitISQED24,

  author = {Surajit Das and Hetang Patel and Chandan Karfa and Kartheek Bellamkonda and Rahul Peddaiahgari Reddy and Disha Puri and Anshul Jain and Arijit Sur and Pradip Prajapati},

  title = {RTL Simulation Acceleration with Machine Learning Models},

  booktitle = {25th International Symposium on Quality Electronic Design (ISQED'24)},

  year = {2024}

}

  4. Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha and Chandan Karfa, “SRIL: Securing Registers from Information Leakage at Register Transfer Level,” in 37th International Conference of VLSI Design (VLSID 2024), 2024.
    [BibTeX] 

    
@inproceedings{PriyankaVLSID24,

  author = {Priyanka Panigrahi and Vignesh Ravichandra Rao and Thockchom Birjit Singha and Chandan Karfa},

  title = {SRIL: Securing Registers from Information Leakage at Register Transfer Level},

  booktitle = {37th International Conference of VLSI Design (VLSID 2024)},

  year = {2024}

}

  5. Priyanka Panigrahi and Chandan Karfa, “An Investigation into the Security of Register Allocation with Spilling and Splitting,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 300-305, 2023.
    [BibTeX] 

    
@inproceedings{PriyankaISVLSI23,

  author = {Priyanka Panigrahi and Chandan Karfa},

  title = {An Investigation into the Security of Register Allocation with Spilling and Splitting},

  booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},

  year = {2023},

  pages = {300-305},

  doi = {https://doi.org/10.1109/ISQED54688.2022.9806218}

}

  6. Praveen Karmakar, Divyandhu Nauni and Chandan Karfa, “Analyzing Area and Latency Overhead in C and RTL Locked Designs,” in IEEE Asia Pacific Conference On Circuits And Systems (APCCAS 2023), 2023.
    [BibTeX] 

    
@inproceedings{PraveenAPCCAS23,

  author = {Praveen Karmakar and Divyandhu Nauni and Chandan Karfa},

  title = {Analyzing Area and Latency Overhead in C and RTL Locked Designs},

  booktitle = {IEEE Asia Pacific Conference On Circuits And Systems (APCCAS 2023)},

  year = {2023}

}

  7. Arshdeep Kaur, Sayandeep Saha, Chandan Karfa and Debdeep Mukhopadhyay, “Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking,” in 2022 23rd International Symposium on Quality Electronic Design (ISQED), pp. 1-6, 2022.
    [BibTeX] 

    
@inproceedings{ArshDeepISQED2022,

  author = {Kaur, Arshdeep and Saha, Sayandeep and Karfa, Chandan and Mukhopadhyay, Debdeep},

  title = {Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking},

  booktitle = {2022 23rd International Symposium on Quality Electronic Design (ISQED)},

  year = {2022},

  pages = {1-6},

  doi = {https://doi.org/10.1109/ISQED54688.2022.9806219}

}

  8. Mohammed Abderehman, Rakesh Theegala Reddy and Chandan Karfa, “DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis,” in 23rd International Symposium on Quality Electronic Design (ISQED), pp. 64-70, 2022.
    [BibTeX] 

    
@inproceedings{MohammedISQED22,

  author = {Mohammed Abderehman and Rakesh Theegala Reddy and Chandan Karfa},

  title = {DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis},

  booktitle = {23rd International Symposium on Quality Electronic Design (ISQED)},

  year = {2022},

  pages = {64-70},

  doi = {https://doi.org/10.1109/ISQED54688.2022.9806218}

}

  9. Gagan Gayari, Chandan Karfa and Prithwjit Guha, “GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking,” in 32nd edition of GLSVLSI 2022, 2022.
    [BibTeX] [URL] 

    
@inproceedings{GaganGLSVLSI2022,

  author = {Gagan Gayari and Chandan Karfa and Prithwjit Guha},

  title = {GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking},

  booktitle = {32nd edition of GLSVLSI 2022},

  publisher = {Association for Computing Machinery},

  year = {2022},

  url = {https://doi.org/10.1145/3526241.3530362},

  doi = {https://doi.org/10.1145/3526241.3530362}

}

  10. Mohammed Abderehman, Rupak Gupta, Theegala Rakesh Reddy and Chandan Karfa, “BLAST: Belling the Black-Hat High-level Synthesis Tool,” in International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2022, July 2022.
    [BibTeX] 

    
@inproceedings{mohammedcodes22,

  author = {Mohammed Abderehman and Rupak Gupta and Theegala Rakesh Reddy and Chandan Karfa},

  title = {BLAST: Belling the Black-Hat High-level Synthesis Tool},

  booktitle = {International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2022},

  publisher = {IEEE},

  year = {2022}

}

  11. T.M. Abdul Khader, Nilotpola Sarma and Chandan Karfa, “ImageSpec: Efficient High-Level Synthesis of Image Processing Applications,” in Euromicro Conference on Digital Systems Design 2022 (DSD22), July 2022.
    [BibTeX] 

    
@inproceedings{nilotpoladsd22,

  author = {TM Abdul Khader and Nilotpola Sarma and Chandan Karfa},

  title = {ImageSpec: Efficient High-Level Synthesis of Image Processing Applications},

  booktitle = {Euromicro Conference on Digital Systems Design 2022 (DSD22)},

  publisher = {IEEE},

  year = {2022}

}

  12. Priyanka Panigrahi, Abhik Paul and Chandan Karfa, “Quantifying Information Leakage for Security Verification of Compiler Optimizations,” in International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) 2022, July 2022.
    [BibTeX] 

    
@inproceedings{priyankacases22,

  author = {Priyanka Panigrahi and Abhik Paul and Chandan Karfa},

  title = {Quantifying Information Leakage for Security Verification of Compiler Optimizations},

  booktitle = {International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES) 2022},

  publisher = {IEEE},

  year = {2022}

}

  13. Mohammed Abderehman and Chandan Karfa, “An SMT-based Reverse Engineering of Register Allocation in High-level Synthesis,” in 5th International Symposium on Devices, Circuits and Systems (ISDCS 2022), March 2022.
    [BibTeX] 

    
@inproceedings{MohammedISDCS22,

  author = {Mohammed Abderehman and Chandan Karfa},

  title = {An SMT-based Reverse Engineering of Register Allocation in High-level Synthesis},

  booktitle = {5th International Symposium on Devices, Circuits and Systems (ISDCS 2022)},

  publisher = {Springer},

  year = {2022}

}

  14. Debabrata Senapati, Arnab Sarkar and Chandan Karfa, “Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems.,” in 23rd International Conference on Distributed Computing and Networking, January 2022.
    [BibTeX] 

    
@inproceedings{DebabrataICDCN22,

  author = {Debabrata Senapati and Arnab Sarkar and Chandan Karfa},

  title = {Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems.},

  booktitle = {23rd International Conference on Distributed Computing and Networking},

  publisher = {ACM},

  year = {2022}

}

  15. S. Das and C. Karfa, “Deadlock Avoidance in Torus NoC Applying Controlled Move via Wraparound Channels,” in 10th International Symposium on Embedded Computing and System Design (ISED), Jul 2021.
    [BibTeX] 

    
@inproceedings{Surajit2ISED2021,

  author = {S. Das and C. Karfa},

  title = {Deadlock Avoidance in Torus NoC Applying Controlled Move via Wraparound Channels},

  booktitle = {10th International Symposium on Embedded Computing and System Design (ISED)},

  publisher = {Springer},

  year = {2021}

}

  16. S. Das and C. Karfa, “Formal Modeling and Verification of Starvation-Freedom in NoCs,” in 10th International Symposium on Embedded Computing and System Design (ISED), Jul 2021.
    [BibTeX] 

    
@inproceedings{SurajitISED21,

  author = {S. Das and C. Karfa},

  title = {Formal Modeling and Verification of Starvation-Freedom in NoCs},

  booktitle = {10th International Symposium on Embedded Computing and System Design (ISED)},

  publisher = {Springer},

  year = {2021}

}

  17. D. Senapati, A. Sarkar and C. Karfa, “HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems,” in ACM SIGBED International Conference on Embedded Software (EMSOFT), Jul 2021.
    [BibTeX] 

    
@inproceedings{DebabrataEMSOFT21,

  author = {D. Senapati and A. Sarkar and C. Karfa},

  title = {HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems},

  booktitle = {ACM SIGBED International Conference on Embedded Software (EMSOFT)},

  publisher = {ACM},

  year = {2021}

}

  18. M. Abderrahman, R. Gupta and C. Karfa, “Reverse Engineering Register to Variable Mapping in High-Level Synthesis,” in IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Jul 2021.
    [BibTeX] 

    
@inproceedings{MohammedIsvisi21,

  author = {M. Abderrahman and R. Gupta and C. Karfa},

  title = {Reverse Engineering Register to Variable Mapping in High-Level Synthesis},

  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI},

  publisher = {IEEE},

  year = {2021}

}

  19. Chandan Karfa, T.M. Abdul Khader, Yom Nigam, Ramanuj Chouksey and Ramesh Karri, “HOST: HLS Obfuscations against SMT ATtack,” in 23rd Conference on Design, Automation and Test in Europe (DATE'21), pp. -, March 2021.
    [BibTeX] 

    
@inproceedings{karfaDate2021,

  author = {Chandan Karfa and TM Abdul Khader and Yom Nigam and Ramanuj Chouksey and Ramesh Karri},

  title = {HOST: HLS Obfuscations against SMT ATtack},

  booktitle = {23rd Conference on Design, Automation and Test in Europe (DATE'21)},

  year = {2021},

  pages = {--}

}

  20. Melbin John, Aadil Hoda, Ramanuj Chouksey and Chandan Karfa, “SAT Based Partial Attack on Compound Logic Locking,” in IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) (Best Paper Nomination), pp. 1-6, December 2020.
    [BibTeX] 

    
@inproceedings{karfaAsianHost2020,

  author = {Melbin John and Aadil Hoda and Ramanuj Chouksey and Chandan Karfa},

  title = {SAT Based Partial Attack on Compound Logic Locking},

  booktitle = {IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) (Best Paper Nomination)},

  year = {2020},

  pages = {1-6}

}

  21. Pankaj Kalita, Ramanuj Chouksey and Chandan Karfa, “Automatic Inverse Operation Detection and its Impact in High-level Synthesis,” in 24th International Symposium on VLSI Design and Test (VDAT 2020), pp. 1-4, August 2020.
    [BibTeX] 

    
@inproceedings{karfaVdat2020,

  author = {Pankaj Kalita and Ramanuj Chouksey and Chandan Karfa},

  title = {Automatic Inverse Operation Detection and its Impact in High-level Synthesis},

  booktitle = {24th International Symposium on VLSI Design and Test (VDAT 2020)},

  year = {2020},

  pages = {1-4}

}

  22. Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg and Ramesh Karri, “Is Register Transfer Level Locking Secure Against SAT Attacks?,” in 22nd Conference on Design, Automation and Test in Europe (DATE) 2020, pp. 550–555, March 2020.
    [BibTeX] 

    
@inproceedings{karfaDate2020,

  author = {Chandan Karfa and Ramanuj Chouksey and Christian Pilato and Siddharth Garg and Ramesh Karri},

  title = {Is Register Transfer Level Locking Secure Against SAT Attacks?},

  booktitle = {22nd Conference on Design, Automation and Test in Europe (DATE) 2020},

  year = {2020},

  pages = {550–555}

}

  23. Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, “Formal Verification of Optimizing Transformations During High-level Synthesis,” in Proceedings of the 12th Innovations on Software Engineering Conference (Formerly Known As India Software Engineering Conference), pp. 27:1-27:5, 2019.
    [BibTeX] [URL] 

    
@inproceedings{ramanujIsec19,

  author = {Chouksey, Ramanuj and Karfa, Chandan and Bhaduri, Purandar},

  title = {Formal Verification of Optimizing Transformations During High-level Synthesis},

  booktitle = {Proceedings of the 12th Innovations on Software Engineering Conference (Formerly Known As India Software Engineering Conference)},

  publisher = {ACM},

  year = {2019},

  pages = {27:1--27:5},

  url = {http://doi.acm.org/10.1145/3299771.3299797},

  doi = {https://doi.org/10.1145/3299771.3299797}

}

  24. Priyanka Panigrahi, Rajesh Kumar Jha and Chandan Karfa, “User Guided Register Manipulation in Digital Circuits,” in Proc. 23rd VLSI Design and Test Symposium (VDAT 2019), pp. 468-481, Aug 2019.
    [BibTeX] 

    
@inproceedings{karfaVdat2019,

  author = {Priyanka Panigrahi and Rajesh Kumar Jha and Chandan Karfa},

  title = {User Guided Register Manipulation in Digital Circuits},

  booktitle = {Proc. 23rd VLSI Design and Test Symposium (VDAT 2019)},

  publisher = {Springer},

  year = {2019},

  pages = {468-481}

}

  25. R. Chouksey, C. Karfa and P. Bhaduri, “Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples,” in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), pp. 377-382, Jan 2019.
    [BibTeX] 

    
@inproceedings{ramanujVlsi19,

  author = {R. Chouksey and C. Karfa and P. Bhaduri},

  title = {Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples},

  booktitle = {2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)},

  year = {2019},

  pages = {377-382},

  doi = {https://doi.org/10.1109/VLSID.2019.00083}

}

  26. Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa and Pankaj Kumar Kalita, “Automatic Detection of Inverse Operations while Avoiding Loop Unrolling,” in 40th International Conference on Software Engineering (ICSE 18), May 27 - 3 June 2018, Gothenburg, Sweden, pp. -, 2018.
    [BibTeX] 

    
@inproceedings{icse18,

  author = {Kunal Banerjee and Ramanuj Chouksey and Chandan Karfa and Pankaj Kumar Kalita},

  title = {Automatic Detection of Inverse Operations while Avoiding Loop Unrolling},

  booktitle = {40th International Conference on Software Engineering (ICSE 18), May 27 - 3 June 2018, Gothenburg, Sweden},

  year = {2018},

  pages = {--}

}

  27. Kunal Banerjee and Chandan Karfa, “Compiler-agnostic Translation Validation,” in Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, Hyderabad, India, February 09 - 11, 2018, pp. 22:1, 2018.
    [BibTeX] 

    
@inproceedings{DBLP:conf/indiaSE/BanerjeeK18,

  author = {Kunal Banerjee and Chandan Karfa},

  title = {Compiler-agnostic Translation Validation},

  booktitle = {Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, Hyderabad, India, February 09 - 11, 2018},

  year = {2018},

  pages = {22:1}

}

  28. Ramanuj Chouksey, Chandan Karfa and Purandar Bhaduri, “Translation Validation of Loop Invariant Code Optimizations Involving False Computations,” in VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 767-778, 2017.
    [BibTeX] 

    
@inproceedings{DBLP:conf/vdat/ChoukseyKB17,

  author = {Ramanuj Chouksey and Chandan Karfa and Purandar Bhaduri},

  title = {Translation Validation of Loop Invariant Code Optimizations Involving False Computations},

  booktitle = {VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},

  year = {2017},

  pages = {767--778}

}

  29. Surajit Das, Chandan Karfa and Santosh Biswas, “xMAS Based Accurate Modeling and Progress Verification of NoCs,” in VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 792-804, 2017.
    [BibTeX] 

    
@inproceedings{DBLP:conf/vdat/DasKB17,

  author = {Surajit Das and Chandan Karfa and Santosh Biswas},

  title = {xMAS Based Accurate Modeling and Progress Verification of NoCs},

  booktitle = {VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},

  year = {2017},

  pages = {792--804}

}

  30. Chandan Karfa, “Automatic register balancing in model-based high-level synthesis,” in 2015 6th Asia Symposium on Quality Electronic Design (ASQED), pp. 43-49, Aug 2015.
    [BibTeX] 

    
@inproceedings{karfa2015automatic,

  author = {Chandan Karfa},

  title = {Automatic register balancing in model-based high-level synthesis},

  booktitle = {2015 6th Asia Symposium on Quality Electronic Design (ASQED)},

  publisher = {IEEE},

  year = {2015},

  pages = {43--49}

}

  31. Chandan Karfa and Sheetal Jain, “On multi-cycle path support in model based high-level synthesis,” in Students' Technology Symposium (TechSym), 2014 IEEE, pp. 253-258, Feb 2014.
    [BibTeX] 

    
@inproceedings{karfa2014multi,

  author = {Chandan Karfa and Sheetal Jain},

  title = {On multi-cycle path support in model based high-level synthesis},

  booktitle = {Students' Technology Symposium (TechSym), 2014 IEEE},

  publisher = {IEEE},

  year = {2014},

  pages = {253--258}

}

  32. Chandan Karfa, K. Banerjee, D. Sarkar and C. Mandal, “Experimentation with SMT Solvers and Theorem Provers for Verification of Loop and Arithmetic Transformations,” in Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop, pp. 3:1-3:4, 2013.
    [BibTeX] 

    
@inproceedings{Karfa:2013:icare,

  author = {Karfa, Chandan and Banerjee, K. and Sarkar, D. and Mandal, C.},

  title = {Experimentation with SMT Solvers and Theorem Provers for Verification of Loop and Arithmetic Transformations},

  booktitle = {Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop},

  publisher = {ACM},

  year = {2013},

  pages = {3:1--3:4}

}

  33. Chandan Karfa, Dipankar Sarkar and Chittaranjan A. Mandal, “Verification of KPN Level Transformations,” in 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, pp. 338-343, Jan 2013.
    [BibTeX] 

    
@inproceedings{karfa2013KPN,

  author = {Chandan Karfa and Dipankar Sarkar and Chittaranjan A. Mandal},

  title = {Verification of KPN Level Transformations},

  booktitle = {26th International Conference on VLSI Design and 12th International Conference on Embedded Systems},

  publisher = {IEEE},

  year = {2013},

  pages = {338--343}

}

  34. Kunal Banerjee, Chandan Karfa, Dipankar Sarkar and Chittaranjan A. Mandal, “A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques,” in 2012 International Symposium on Electronic System Design (ISED), pp. 67-71, Dec 2012.
    [BibTeX] 

    
@inproceedings{karfa2012value,

  author = {Kunal Banerjee and Chandan Karfa and Dipankar Sarkar and Chittaranjan A. Mandal},

  title = {A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques},

  booktitle = {2012 International Symposium on Electronic System Design (ISED)},

  publisher = {IEEE},

  year = {2012},

  pages = {67-71}

}

  35. Chandan Karfa, Kunal Banerjee, Dipankar Sarkar and Chitta Mandal, “Equivalence Checking of Array-Intensive Programs,” in 2011 IEEE Computer Society Annual Symposium on VLSI, pp. 313-314, Jul 2011.
    [BibTeX] 

    
@inproceedings{karfa2011equivalencecheck,

  author = {Chandan Karfa and Kunal Banerjee and Dipankar Sarkar and Chitta Mandal},

  title = {Equivalence Checking of Array-Intensive Programs},

  booktitle = {2011 IEEE Computer Society Annual Symposium on VLSI},

  publisher = {IEEE},

  year = {2011},

  pages = {313--314}

}

  36. Chandan Karfa, Chitta Mandal and Dipankar Sarkar, “Verification of Register Transfer Level Low Power Transformations,” in 2011 IEEE Computer Society Annual Symposium on VLSI, pp. 313-314, Jul 2011.
    [BibTeX] 

    
@inproceedings{karfa2011verificationregister,

  author = {Chandan Karfa and Chitta Mandal and Dipankar Sarkar},

  title = {Verification of Register Transfer Level Low Power Transformations},

  booktitle = {2011 IEEE Computer Society Annual Symposium on VLSI},

  publisher = {IEEE},

  year = {2011},

  pages = {313--314}

}

  37. Chandan Karfa, Dipankar Sarkar and Chittaranjan A. Mandal, “Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques,” in IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 428-433, Jul 2010.
    [BibTeX] 

    
@inproceedings{karfa2010dataflowdriven,

  author = {Chandan Karfa and Dipankar Sarkar and Chittaranjan A. Mandal},

  title = {Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques},

  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI},

  publisher = {IEEE},

  year = {2010},

  pages = {428--433}

}

  38. Chandan Karfa, Dipankar Sarkar and Chitta Mandal, “Verification of Data-path and Controller Generation Phase of High-level Synthesis,” in 15th International Conference on Advanced Computing and Communications (ADCOM 2007), pp. 315-320, Dec 2007.
    [BibTeX] 

    
@inproceedings{karfa2007verificationdata,

  author = {Chandan Karfa and Dipankar Sarkar and Chitta Mandal},

  title = {Verification of Data-path and Controller Generation Phase of High-level Synthesis},

  booktitle = {15th International Conference on Advanced Computing and Communications (ADCOM 2007)},

  publisher = {IEEE},

  year = {2007},

  pages = {315-320}

}

  39. Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal and Chris Reade, “Hand-in-hand Verification of High-level Synthesis,” in Proceedings of the 17th ACM Great Lakes Symposium on VLSI, pp. 429-434, Mar 2007.
    [BibTeX] 

    
@inproceedings{Karfa2007hand,

  author = {Chandan Karfa and Dipankar Sarkar and Chittaranjan A. Mandal and Chris Reade},

  title = {Hand-in-hand Verification of High-level Synthesis},

  booktitle = {Proceedings of the 17th ACM Great Lakes Symposium on VLSI},

  publisher = {ACM},

  year = {2007},

  pages = {429--434}

}

  40. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar and Chris Reade, “Register Sharing Verification During Data-Path Synthesis,” in Computing: Theory and Applications, 2007. ICCTA '07. International Conference on,, pp. 135-140, Mar 2007.
    [BibTeX] 

    
@inproceedings{karfa2007registerrohtua,

  author = {Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar and Chris Reade},

  title = {Register Sharing Verification During Data-Path Synthesis},

  booktitle = {Computing: Theory and Applications, 2007. ICCTA '07. International Conference on,},

  publisher = {IEEE},

  year = {2007},

  pages = {135--140}

}

  41. S. Biswas, C. Karfa, H. Kanwar, D. Sarkar, S. Mukhopadhyay and A. Patra, “Fairness of transitions in diagnosability analysis of hybrid systems,” in 2006 American Control Conference, pp. 6, Jun 2006.
    [BibTeX] 

    
@inproceedings{karfa2006hybrid,

  author = {S. Biswas and C. Karfa and H. Kanwar and D. Sarkar and S. Mukhopadhyay and A. Patra},

  title = {Fairness of transitions in diagnosability analysis of hybrid systems},

  booktitle = {2006 American Control Conference},

  publisher = {IEEE},

  year = {2006},

  pages = {6}

}

  42. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota and Chris Reade, “A Formal Verification Method of Scheduling in High-level Synthesis,” in 7th International Symposium on Quality Electronic Design (ISQED'06), pp. 71-78, Mar 2006.
    [BibTeX] 

    
@inproceedings{karfa2006verificationhighlevel,

  author = {Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar and S. R. Pentakota and Chris Reade},

  title = {A Formal Verification Method of Scheduling in High-level Synthesis},

  booktitle = {7th International Symposium on Quality Electronic Design (ISQED'06)},

  publisher = {IEEE},

  year = {2006},

  pages = {71--78}

}

  43. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota and Chris Reade, “Verification of Scheduling in High-level Synthesis,” in IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), pp. 141-146, Mar 2006.
    [BibTeX] 

    
@inproceedings{karfa2006verificationsched,

  author = {Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar and S. R. Pentakota and Chris Reade},

  title = {Verification of Scheduling in High-level Synthesis},

  booktitle = {IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)},

  publisher = {IEEE},

  year = {2006},

  pages = {141--146}

}

  44. C. Karfa, J. S. Reddy, C. R. Mandal, D. Sarkar and S. Biswas, “SAST: An interconnection aware high-level synthesis tool,” in Proc. 9th VLSI Design and Test Symposium, Bangalore, pp. 285-292, Aug 2005.
    [BibTeX] 

    
@inproceedings{karfa2005interconnection,

  author = {C. Karfa and J.S. Reddy and C. R. Mandal and D. Sarkar and S Biswas},

  title = {SAST: An interconnection aware high-level synthesis tool},

  booktitle = {Proc. 9th VLSI Design and Test Symposium, Bangalore},

  publisher = {IEEE},

  year = {2005},

  pages = {285--292}

}