Priyanka Panigrahi
July 2017-
Area: Security Analysis of Compiler Optimizations
Email: priya176101006@iitg.ac.in
Nilotpola Sarma
January 2021-
Area: Security Verification
Email: s.nilotpola@iitg.ac.in
Praveen Karmakar (Joint supervision with Dr. Sukanta Bhattacharjee)
July 2022-
Area: Hardware Security
Email: pkarmakar@iitg.ac.in
Akash Lal Dutta (Joint supervision with Dr. Sukanta Bhattacharjee)
July 2022-
Area: ML for EDA
Email: akash@iitg.ac.in
Bhabesh Mali
July 2023-
Area: ML for Security
Email: m.bhabesh@iitg.ac.in
Graduated Ph.D. Students
Dr. Ramanuj Chouksey
August 2016- August 2020
Theis Title: Formal Verification and Security Analysis of High-level Synthesis
Email: r.chouksey@iitg.ac.in
Next Position: Lead Engineer at Cadence
Dr. Surajit Das (Joint supervision with Dr. Santosh Biswas)
August 2016- May 2022
Thesis Title: Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms
Email: d.surajit@iitg.ac.in
Next Position: Intel India Post-Doctoral Fellow.
Dr. Mohammed Aderehman Adem
January 2018- October 2022
Thesis Title: Reverse-Engineering of High-level Synthesis and Its Applications
Email: ma.adem@iitg.ac.in
Next Position: Faculty at Defence Engineering College, Ethiopia.
Pavan Ganesh Jeereddy (Joint supervision with Dr. Santosh Biswas)
2016-2018
Broad Area: NoC Verification: Deadlock Detection Using by Bottom Up Approach
Ajinkya Sanjay Mankar (Joint supervision with Dr. Santosh Biswas)
2016-2018
Broad Area: NoC Verification: Deadlock Detection Using Dynamic Graph Generation
Graduated B.Tech. Students
Tanay Maheshwari
2019-2023
Thesis: Counter Example Generation for Insecure Transformation of Compiler Optimizations
Vignesh Ravichandra Rao
2019-2023
Thesis: Power Side Channel Secure RTL Design
Marpina Bharani
2019-2023
Thesis: Scalable attack on Combinational Circuits
Ritik Kumar
2019-2023
Thesis: High level Syntehsis and Optimization of ML Models
Bodavula Teja Sai Srikar
2019-2023
Thesis: Translation Validation of High Level Synthesis
Saaketh Gunti
2019-2023
Thesis: SAT Based Attacks on Machine Learning Models
Rahul Reddy Peddaiahgari
2019-2023
Thesis: Predicting outputs of RTL circuits using Machine Learning
Naresh Bharasagar
2018-2022
Thesis: Formal Verification of Security Countermeasures Against Power
Side-Channel Attacks
Pooja Gajendra Bhagat
2018-2022
Thesis: Security-Aware DAG Scheduler for Heterogeneous Distributed Systems
Param Aryan Singh
2018-2022
Thesis: Hardware Security against IP Theft
Kousik Rajesh
2018-2022
Thesis: Temperature-aware Makespan Minimizing DAG Scheduler for
Heterogeneous Distributed Systems
Dristiron Saikia
2018-2022
Thesis: Security Analysis of C/C Programs
Shivam Kumar Agarwal
2018-2022
Broad Area: Formal Verification Of Security Measures Against Timing Side-Channel Attacks
Soumik Paul
2017-2021
Broad Area: Hardware Trojan Detection in Post-silicon Validation
Vemuri Sahithya
2017-2021
Broad Area: Analysis of Information Leakage in LLVM Compiler
T. Rakesh Reddy
2017-2021
Broad Area: Data-driven Equivalence Checking