Chandan Karfa

Ongoing Ph.D. Students

Nilotpola Sarma
January 2021-
Area: Security Verification
Email: s.nilotpola@iitg.ac.in

Praveen Karmakar
July 2022-
Area: Hardware Security
Email: pkarmakar@iitg.ac.in
(Joint supervision with Dr. Sukanta Bhattacharjee)

Akash Lal Dutta
July 2022-
Area: ML for EDA
Email: akash@iitg.ac.in
(Joint supervision with Dr. Sukanta Bhattacharjee)

Bhabesh Mali
July 2023-
Area: ML for EDA
Email: m.bhabesh@iitg.ac.in
(Joint supervision with Dr. Sukanta Bhattacharjee)

E Bhawani Eswar Reddy
July 2023-
Area: Security of ML
Email: r.eddula@iitg.ac.in
(Joint supervision with Dr. Sukanta Bhattacharjee)

Innocent Dengkhw Mochahari
July 2024-
Area: ML for EDA
Email: innocent@iitg.ac.in
(Joint supervision with Dr. Sukanta Bhattacharjee)

Graduated Ph.D. Students

Dr. Priyanka Panigrahi
July 2017- November 2023
Area: Security Verification of Compiler Optimizations: An Information Flow Perspective
Email: priya176101006@iitg.ac.in

Dr. Debabrata Senapati (Joint supervision with Dr. Arnab Sarkar)
July 2017- June 2023
Thesis: Efficient Techniques for Scheduling DAG Applications in Distributed Environments
Email: debab176101003@iitg.ac.in
Next Position: Assiatant Professor, SRM University.

Dr. Mohammed Aderehman Adem
January 2018- October 2022
Thesis Title: Reverse-Engineering of High-level Synthesis and Its Applications
Email: ma.adem@iitg.ac.in
Next Position: Faculty at Defence Engineering College, Ethiopia.

Dr. Surajit Das (Joint supervision with Dr. Santosh Biswas)
August 2016- May 2022
Thesis Title: Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms
Email: d.surajit@iitg.ac.in
Next Position: Intel India Post-Doctoral Fellow.

Dr. Ramanuj Chouksey
August 2016- August 2020
Theis Title: Formal Verification and Security Analysis of High-level Synthesis
Email: r.chouksey@iitg.ac.in
Next Position: Lead Engineer at Cadence

Ongoing M.Tech. Students

Mani Deep G
2024-2026
Thesis:

Shipon Nandy
2024-2026
Thesis:

Tapish Patidar
2024-2026
Thesis:

Tellabiyyam Abhilash
2024-2026
Thesis:

Naman Baveja
2024-2026
Thesis:

Chirag Gajbhiye
2024-2026
Thesis:

Ongoing B.Tech. Students

ADITYA KUMAR
2022-2026
Thesis:

BRAJESH MUWEL
2022-2026
Area:

KOTHA HITESH
2022-2026
Thesis: ML for Logic Locking

KOVID JUNEJA
2022-2026
Thesis: ML based Simulation Acceleration

MOHD FAIZ
2022-2026
Thesis: Logic Synthesis

PATEL DHYEY SANJAYKUMAR
2022-2026
Area: ML for EDA

SHASHWAT SHANKAR
2022-2026
Thesis: ML for EDA

SHOBHIT GUPTA
2022-2026
Thesis: EDA

SHUBHRANSHU PANDEY
2022-2026
Thesis: Logic Synthesis

VIDHI ARORA
2022-2026
Thesis: Security Verification

VIKRANT
2022-2026
Thesis: Security Verification

PARV AGGARWAL
2022-2026
Thesis: Security Verification

Many of the MTech and BTech students are coguided with Dr. Sukanta Bhattacharjee.

Graduated M.Tech. Students

Harshita Rakesh Mishra
2023-2025
Thesis: Protecting ML models from Physical Side Channel Attacks via Masking

Navdeep Patel
2023-2025
Thesis: Power Side-Channel Secure Register Transfer Level Design using Ad-hoc Techniques

Mukesh Barpete
2023-2025
Thesis: BDD Based Attack on Logic Locking

Sunny Priyadarshi
2023-2025
Thesis: RTL Information Leakage Analysis and its Application in Analysis of High-level Synthesis Security

Nupur Brahmanya
2023-2025
Thesis: Design Space Exploration of Gadget-based Masked Hardware

Manish Joshi
2023-2025
Thesis: Efficient High-Level Synthesis of Post Quantum Cryptography Algorithms

Vaishali Chaudhari
2022-2024
Thesis: Formal Verification of PSCA Security of High Level Synthesis Generated Cryptographic Design

Anuj Singh Thakur
2022-2024
Thesis: Power Side-Channel Secure Register Transfer Level Design

Karthik Maddala
2022-2024
Thesis: Exploring Advanced Verification Techniques: From Security Verification of LLVM, Hardware Fuzzing and Automated Assertion Generation

Debarpan Jana (with Dr. Sukanta Bhattacharjee)
2022-2024
Thesis: An SMT based Model Extraction Attack on Neural Networks

Ayush Mandloi (with Dr. Sukanta Bhattacharjee)
2022-2024
Thesis: An Oracle Guided Attack on State Space Obfuscation Technique

Jatin Gupta (Part time student)
2021-2024
Thesis: Statistical Attack on Logic Locked Designs with Dishonest Oracle

Divyanshu Nauni
2021-2023
Thesis: Logic Locking: Analysing the Area and Latency Overhead of Locked Designs

Prosenjit Biswas
2021-2023
Thesis: C to RTL Equivalence Checking

Rittick Mondal
2021-2023
Thesis: Scalable SMT Attack on Higher Level Locking

Shubham Sachan (Jointly with Dr. Prithwijit Guha)
2021-2023
Thesis: Predicting Robustness of Logic Locking

Subham Das (Part time student)
2020-2023
Thesis: Attacks on locked Combinational and Sequential circuits

Mukul Chaturvedi
2020-2022
Thesis: Verification of Dataflow Optimization in Array-Intensive Programs

Abhik Paul
2020-2022
Thesis: Information Leakage Analysis of Compiler Optimizations

Navjot Singh
2020-2022
Broad Area: Logic Encryption at Higher Abstraction Level

Rupak Gupta
2019-2021
Thesis: Hardware Trojan Detection in High-level Synthesis Generated RTLs

Jayprakash Patidar
2019-2021
Thesis: An RTL-to-C Reverse Engineering based Fast Simulation Framework for High-level Synthesis

Arshdeep Kaur
2019-2021
Thesis: A Statistical Approach to Measure Robustness of Gate-Level Logic Locking

Gagan Gayari (Jointly with Dr. Prithwijit Guha)
2019-2021
Thesis: Genetic Algorithm based Attack on Register Transfer Level Locking

Jay Oza
2018-2020
Broad Area: Fast Simulation of HLS

Yom Nigam
2018-2020
Broad Area: RTL Locking

SAMUJJAL DAS
2017-2019
Broad Area: Property Checking in Business Process Model

SACHIN KUMAR MADDHESHIYA
2017-2019
Broad Area: Equivalence Checking

SUVARIYA AMIT ASHOKBHAI (Joint supervision with Dr. Santosh Biswas)
2017-2019
Broad Area: NoC Verification: Deadlock Detection CFSM

RAJESH KUMAR JHA (Joint supervision with Dr. Santosh Biswas)
2017-2017
Broad Area: DSL specific HLS

Pankaj Kumar Kalita
2016-2018
Broad Area: Equivalence Checking

Pavan Ganesh Jeereddy (Joint supervision with Dr. Santosh Biswas)
2016-2018
Broad Area: NoC Verification: Deadlock Detection Using by Bottom Up Approach

Ajinkya Sanjay Mankar (Joint supervision with Dr. Santosh Biswas)
2016-2018
Broad Area: NoC Verification: Deadlock Detection Using Dynamic Graph Generation

Graduated B.Tech. Students

Himanshi Gautam
2021-2025
Thesis: ML for EDA

Yash Raj Singh
2021-2025
Area: Attack on Sequential Logic Locking

Satyarth Gupta
2021-2025
Thesis: ML for Logic Locking

Ankita Kanoji
2021-2025
Thesis: ML based Simulation Acceleration

Kshitij Maurya
2021-2025
Thesis: Logic Synthesis

$2021-2025\n$

Bussa Sai Santhosh
2021-2025
Area: ML for EDA

Bhogi Sai Sathwik
2021-2025
Thesis: ML for EDA

Meghna Battu
2021-2025
Thesis: EDA

Harshit Seksaria
2021-2025
Thesis: Logic Synthesis

B Vijesh R Bhat
2021-2025
Thesis: Security Verification

Dhruv Patel
2021-2025
Thesis: Security Verification

G. Sai Ram Moham
2020-2024
Thesis: Protection Against Scan-Chain-Based Model Extraction Attacks (Jointly with Dhruv)

Dhruv Shah
2020-2024
Area: Security fo ML Model

Sujeet Narayan Kamble
2020-2024
Thesis: Power Side Channel Secure RTL Design

Chandrabhushan Reddy
2020-2024
Thesis: ML Guided Cut Choices for ASIC Technology Mapping (jointly with Harsh)

Harshwardhan Bhakkad
2020-2024
Area: ML for EDA

Anmoldeep Singh
2020-2024
Thesis: Attacks on Combinational and EFPGA Logic Locking (jointly with Kartik)

Kartik Sharma
2020-2024
Area: Logic Locking

M. Samson
2020-2024
Thesis: Identifying Information Leakage in RTL Design

Hetang Patel
2020-2024
Thesis: Speedup of RTL Simulation Using Machine Learning Techniques

Tanay Maheshwari
2019-2023
Thesis: Counter Example Generation for Insecure Transformation of Compiler Optimizations

Vignesh Ravichandra Rao
2019-2023
Thesis: Power Side Channel Secure RTL Design

Marpina Bharani
2019-2023
Thesis: Scalable attack on Combinational Circuits

Ritik Kumar
2019-2023
Thesis: High level Syntehsis and Optimization of ML Models

Bodavula Teja Sai Srikar
2019-2023
Thesis: Translation Validation of High Level Synthesis

Saaketh Gunti
2019-2023
Thesis: SAT Based Attacks on Machine Learning Models

Rahul Reddy Peddaiahgari
2019-2023
Thesis: Predicting outputs of RTL circuits using Machine Learning

Naresh Bharasagar
2018-2022
Thesis: Formal Verification of Security Countermeasures Against Power Side-Channel Attacks

Pooja Gajendra Bhagat
2018-2022
Thesis: Security-Aware DAG Scheduler for Heterogeneous Distributed Systems

Param Aryan Singh
2018-2022
Thesis: Hardware Security against IP Theft

Kousik Rajesh
2018-2022
Thesis: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems

Dristiron Saikia
2018-2022
Thesis: Security Analysis of C/C Programs

Shivam Kumar Agarwal
2018-2022
Broad Area: Formal Verification Of Security Measures Against Timing Side-Channel Attacks

Soumik Paul
2017-2021
Broad Area: Hardware Trojan Detection in Post-silicon Validation

Vemuri Sahithya
2017-2021
Broad Area: Analysis of Information Leakage in LLVM Compiler

T. Rakesh Reddy
2017-2021
Broad Area: Data-driven Equivalence Checking

Rajanala Harshavardhan Reddy
2017-2021
Broad Area: Logic Locking

Rashi Singh (Jointly with Dr. S. Bhattacharjee)
2017-2021
Broad Area: Compiler Security

Aadil Hoda
2016-2020
Broad Area: Logic Locking

Shimona Verma
2016-2020
Broad Area: Hordware Trojan Detection

Abhishek Bhardwaj
2016-2020
Broad Area: Equivalence Checking of Programs

Abhisheh Suryavanshi
2016-2020
Broad Area: HLS Obfuscation

HARSHIT BANSAL
2015-2019
Broad Area: Verification of Deep Neural Networks

MAYANK YADAV
2015-2019
Broad Area: Verification of Deep Neural Networks

AYUSH SONI
2015-2019
Broad Area: Deep Steganography

AYUSH SINGH
2015-2019
Broad Area: Verification of Database Driven Applications

Manish Kumar Regar
2014-2018
Broad Area: Bottom-up Equivalence Checking

Shah Het Jageshkumar
2014-2018
Broad Area: High-level Synthesis

Datir Vivek Prabhakar
2014-2018
Broad Area: High-level Synthesis

Abhisheh Kumar (working with Dr. Deepak Garg (MPI))
2014-2018
Broad Area: Type systems and secure compilation of web assembly.

Jayesh Mathur (Jointly with Dr. Santosh Biswas)
2014-2018
Broad Area: Loop Invariant Generation

Ravi Kumar
2013-2017
Area: Program Equivalence using CVC4

Jitendra Choudhary
2013-2017
Area: Program Equivalence using CVC4 (joint project with Ravi Kumar)

Siddharth Kumar
2013-2017
Area: Verification of Testability Transformations

Pallavi Yellamelli (Jointly with Dr. Sharmistha Banerjee (DoD))
2013-2017
Area: Design and Development of a Material Selection Software