CS224 (Hardware Lab) Jan 2023- Apr 2023 (Instructor : A Sahu)

Timing and venue : Tuesday 2.00PM to 5.00PM, Hardware Lab, CSE, Ground Floor, Extension Building
Group and Marks : [[ Group Structure Scan.PDF ]]

Verilog HDL Tutorials : Tutorial class will happens on E1 Slot Wednesday 4-5PM and Thirsday 4-5PM Room No 5001
  1. Tutorial 1: Tutorial 1 PDF
  2. Tutorial 2: Tutorial 2 PDF
  3. Tutorial 3: Tutorial 3 (Sequential Design, Counter, Structural/Data Flow/behavioral Model) PDF
  4. Tutorial 4: Tutorial 4 (FSM Implementation Structural/behavioral Model) PDF
  5. Tutorial 5: Tutorial 5 (RTL Design, and Memory/DSP Inference Code) PDF
Verilog HDL Book: Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis , 2nd Edition, PDF Version
Verilog Tutorial by Navabi : rtl-verilog-navabi.pdf
Sl No and Demo Date Weight Part I Part II
1 (17th Jan) 10% (5+5) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF, [[A1 Evaluated Sheet]]
2 (31st Jan) 14% (7+7) Counter and Counter based Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF [[A2 Evaluated Sheet]]
3 (21st Feb) 16% (8+8) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF [[ A3 Evaluated Sheet ]]
4 (28th Mar) 16% Design using FPGA and Xillnx Soft A4: Assignment Statement PDF [[A4 Evaluated Sheet ]]
5 18% Design using FPGA and Xillnx Soft A5: Assignment Statement PDF, cache.cpp and patterson_book_Ch7.pdf [[A5 Evaluated Sheet ]]
6 (TBD) 26% Design using FPGA and Xillnx Soft AssgnStmt-06.pdf and Mem-Cache-DRAM.cpp [[A6 Evaluated Sheet]]

These ICs are available in our HW Lab ICs-HWLAB-CS224.pdf
You can take help from TAs. All the TAs and Instructor of CS223 will be available in lab timing. You can ask TAs or Raktajit Pathak (Room CSE H101) or Bhriguraj Borah (Room CSE Server Room) about licensing and installation of ISE software. Bread board and required ICs may be issued from Hemanta Nath (Hardware Lab).
Demo and Help Files for PC-FPGA-USB communications

Xilinx ISE download, installation and license help is here

Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used,(e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.

And for HDL code: the quality will be based on FPGA utilization (Synthesis Report: optimized number of LUTs, register, Minimum Clock), coding style, performance and comments

General rules:
  1. There will be Six assignments: 3 assignments before Mid Semester and 3 after the mid semester
  2. Weights of assignments: A1(10%)+A2(14%)+A3(16%)+A4(16%)+A5(18%)+A6(26%)
  3. Copy of code will lead to Fail Grade to whole group: both source and destination, if you are copying from any other sources (Internet/Googling), you need to ensure that no other group copy the same from that sources :)
  4. Your source code will be checked with plagarism check software TurnitIn/MOSS. You need to submit/send the source code just after the demo or TA/Evaluator will collect the code at the time of Demo.
  5. We will issue up to two FPGA Boards (one BASYS/one ZYBO/one ATLYS/one Nexys A7) for each group for the whole semester. You need to keep the board with you for the whole semester. Based on your requirement, please issue the board from Lab in charge.
  6. Instructor and TAs will be available in Lab at Lab hours: you can clarify your doubt at Lab hours. We don't take attendance in Lab hours. It is not mandatory to stay in Lab in the Lab hours, but you need to show your demo before deadline.