CS223 (Hardware Lab) Jan 2017- Apr 2017 (Instructors : A Sahu and Chandan Karfa)
Timing and venue : Friday 2.00PM to 5.00PM Hardware Lab, CSE,
[[ Group Structure ]]
TAs: Manojit Ghose (PhD), Sukanta Dey (PhD), Pradeep Sharma (PhD),
- Assignment 4 : Weightage=25 %Marks, (Demo will be on 19st April 2017 and Left over Demo will be on 21 April 2017))
Matrix Multiplication using FPGA Assignment Statement PDF
- You may use part of Assignment 3 for PC to FPGA communication.
- You need to use block ram to store matrix A and B (partly). block ram inferable example code can be found here demo4.vhd and synthesis report for this vhdl file Synthesis Report
- You should take benefit of parallelism of matrix multiplication in hardware, you may create/instantiate many DOT product modules.
- At the time of demo, we can see the output C matrix data, grading will be based on quality of HDL code in term of performance and resource usage.
- Assignment 3 : Weightage=25 %Marks, (Demo will be on 31st March 2017))
Low Pass Filtering of Image using FPGA
- In this assignment, you need to communicate between PC/Desktop and FPGA board. Send image data from PC to FPGA, do the image filtering operation there in FPGA and return the computed image data.
- Sample C code (for 24 bit BMP image) and test image can be found here LPF code and test image
- Image data read and write need to be done in C, actual low pass filtering need to be done on FPGA
- In low pass filter code: for any index value (i and j), you require 27 array read and 3 array write operations. You need to design your HDL in a such way that you should be able to compute the image filtering efficiently. Need to know, how to store the data in block rams FPGA and accessing them efficiently.
- Some help regarding PC-FPGAlink in Linux environment README PC-FPGA link and Download libfpgalink-20120621-CS223.tgz
- Demo VHDL code and C code for PC to FPGA communication is available at PC-FPGA-USB/
- At the time of demo, we can see the input and output image, grading will be based on quality of HDL code in term of performance and resource usage
- Assignment 2 : Weightage=20 %Marks, Time= 9 Lab Hours (Demo will be on 17th and 24th Feb 2017))
Design and implement a 8 bit unsigned multiplier (using ICs and breadbard) [[Motivation: Experiment with Digital Components]] and implementing BIG operators using HDL
Assignment statement for Assignment II
- Assignment 1 : Weightage=15 %Marks, Time= 9 Lab Hours (Demo will be on 3rd Lab (on 27th Jan 2017))
Design and Demonstration of working of 4 bit Counter using 4 Flip Flops [[Motivation: Experiment with Digital Components]]
- [50% Marks] Design and Demonstration 4 bit counter using 4 Flip Flops using chips and breadboard. You are not allowed to use inbuilt counter. If your want you can show out put using LEDs of breadboard or use seven segment LEDS to show/demonstrate the output.
- [ 50% Marks] Design two VHDL models of the same 4 bit counter (a) using FSM with behavioral model and (b) using component model using Flip Flops. Simulate your in Xilinx ISE/Vivado and finally download your design to Digilent ATLYS or Digilent BASYS 3 FPGA board and demonstrate.
These ICs are available in our HW Lab ICs-HWLAB-CS223.pdf
You can take help from TAs. All the TAs and Instructor of CS223 will be available in lab timing. You can ask TAs or Raktajit Pathak (Room CSE H101) or Bhriguraj Borah (Room CSE Server Room) about licensing and installation of ISE software. Bread board and required ICs may be issued from Hemanta Nath (Hardware Lab).
Xilinx ISE download, installation and licence help is here
Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used,(e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.
And for HDL code: the quality will be based on FPGA utilization (Synthesis Report: optimized number of LUTs, register, Minimum Clock), coding style, performance and comments
- There will be 4 assignments: two assignments before Mid Semester and other two after the mid semester, there will be a viva-voice for all individual (not in a group).
- Weights of assignments: A1 15% + A2 20% + A3 25% + A4 25% + Viva Voice Exam (15%)
- Tentative date of Assignment deadlines: 20th Jan for A1, 17th Feb for A2, 15th Mar for A3 and 7th April for A4. Viva-voce exam will be on 20st -22nd April 2017.
- Copy of code will lead to Fail Grade to whole group: both source and destination, if you are copying from any other sources (Internet/Googling), you need to ensure that no other group copy the same from that sources :)
- Your source code will be checked in Plagarism check software TurnitIn/MOSS. You need to submit/send the source code just after the demo or TA/Evaluator will collect the code at the time of Demo.
- We will issue two FPGA Boards (one BASYS and one ATLYS) for each group for the whole semester. You need to keep the board with you for the whole semester.
- Instructor and TAs will be available in Lab at Lab hours: you can clarify your doubt at Lab hours. We don't take attendance in Lab hours. It is not mandatory to stay in Lab in the Lab hours, but you need to show your demo before deadline.