CS223 (Hardware Lab) Jan 2017- Apr 2017 (Instructors : A Sahu and Chandan Karfa)

Timing and venue : Friday 2.00PM to 5.00PM Hardware Lab, CSE,
[[ Group Structure ]]

TAs: Manojit Ghose (PhD), Sukanta Dey (PhD), Pradeep Sharma (PhD),
These ICs are available in our HW Lab ICs-HWLAB-CS223.pdf
You can take help from TAs. All the TAs and Instructor of CS223 will be available in lab timing. You can ask TAs or Raktajit Pathak (Room CSE H101) or Bhriguraj Borah (Room CSE Server Room) about licensing and installation of ISE software. Bread board and required ICs may be issued from Hemanta Nath (Hardware Lab).

Xilinx ISE download, installation and licence help is here

Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used,(e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.

And for HDL code: the quality will be based on FPGA utilization (Synthesis Report: optimized number of LUTs, register, Minimum Clock), coding style, performance and comments

General rules:
  1. There will be 4 assignments: two assignments before Mid Semester and other two after the mid semester, there will be a viva-voice for all individual (not in a group).
  2. Weights of assignments: A1 15% + A2 20% + A3 25% + A4 25% + Viva Voice Exam (15%)
  3. Tentative date of Assignment deadlines: 20th Jan for A1, 17th Feb for A2, 15th Mar for A3 and 7th April for A4. Viva-voce exam will be on 20st -22nd April 2017.
  4. Copy of code will lead to Fail Grade to whole group: both source and destination, if you are copying from any other sources (Internet/Googling), you need to ensure that no other group copy the same from that sources :)
  5. Your source code will be checked in Plagarism check software TurnitIn/MOSS. You need to submit/send the source code just after the demo or TA/Evaluator will collect the code at the time of Demo.
  6. We will issue two FPGA Boards (one BASYS and one ATLYS) for each group for the whole semester. You need to keep the board with you for the whole semester.
  7. Instructor and TAs will be available in Lab at Lab hours: you can clarify your doubt at Lab hours. We don't take attendance in Lab hours. It is not mandatory to stay in Lab in the Lab hours, but you need to show your demo before deadline.