Release 14.7 - xst P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.08 secs --> Reading design: ram_example.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "ram_example.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "ram_example" Output Format : NGC Target Device : xc6slx45-3-csg324 ---- Source Options Top Module Name : ram_example Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "/home/pradeep/Desktop/Untitled Folder/demo4/demo4.vhd" into library work Parsing entity . Parsing architecture of entity . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating entity (architecture ) from library . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "/home/pradeep/Desktop/Untitled Folder/demo4/demo4.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 256x8-bit single-port RAM for signal . Found 256x8-bit single-port RAM for signal . Found 8-bit register for signal . Found 8-bit register for signal . Summary: inferred 2 RAM(s). inferred 16 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 2 256x8-bit single-port RAM : 2 # Registers : 2 8-bit register : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 8-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal
| | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 8-bit | | | mode | read-first | | | clkA | connected to signal | rise | | weA | connected to signal | high | | addrA | connected to signal
| | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- | optimization | speed | | ----------------------------------------------------------------------- Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # RAMs : 2 256x8-bit single-port block RAM : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block ram_example, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Found no macro ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : ram_example.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 2 # GND : 1 # VCC : 1 # RAMS : 2 # RAMB8BWER : 2 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 41 # IBUF : 25 # OBUF : 16 Device utilization summary: --------------------------- Selected Device : 6slx45csg324-3 Slice Logic Utilization: Slice Logic Distribution: Number of LUT Flip Flop pairs used: 0 Number with an unused Flip Flop: 0 out of 0 Number with an unused LUT: 0 out of 0 Number of fully used LUT-FF pairs: 0 out of 0 Number of unique control sets: 0 IO Utilization: Number of IOs: 66 Number of bonded IOBs: 42 out of 218 19% Specific Feature Utilization: Number of Block RAM/FIFO: 1 out of 116 0% Number using Block RAM only: 1 Number of BUFG/BUFGCTRLs: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clk | BUFGP | 2 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: 2.188ns Maximum output required time after clock: 4.800ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk' Total number of paths / destination ports: 36 / 36 ------------------------------------------------------------------------- Offset: 2.188ns (Levels of Logic = 1) Source: address<7> (PAD) Destination: Mram_ram_x (RAM) Destination Clock: Clk rising Data Path: address<7> to Mram_ram_x Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 2 1.222 0.616 address_7_IBUF (address_7_IBUF) RAMB8BWER:ADDRAWRADDR10 0.350 Mram_ram_x ---------------------------------------- Total 2.188ns (1.572ns logic, 0.616ns route) (71.8% logic, 28.2% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk' Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------- Offset: 4.800ns (Levels of Logic = 1) Source: Mram_ram_x (RAM) Destination: data_o_x<7> (PAD) Source Clock: Clk rising Data Path: Mram_ram_x to data_o_x<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ RAMB8BWER:CLKAWRCLK->DOADO7 1 1.650 0.579 Mram_ram_x (data_o_x_7_OBUF) OBUF:I->O 2.571 data_o_x_7_OBUF (data_o_x<7>) ---------------------------------------- Total 4.800ns (4.221ns logic, 0.579ns route) (87.9% logic, 12.1% route) ========================================================================= Cross Clock Domains Report: -------------------------- ========================================================================= Total REAL time to Xst completion: 11.00 secs Total CPU time to Xst completion: 9.97 secs --> Total memory usage is 391792 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 2 ( 0 filtered)