JOHN JOSE

Assistant Professor
Department of Computer Science & Engineering
Indian Institute of Technology Guwahati
Guwahati - 781039, Assam, India

Contact Details

Office: Room Number H-201, CSE Dept, IITG
Phone: 0361- 2583256
Email: johnjose [AT] iitg [DOT] ac [DOT] in
             johnjose004 [AT] gmail [DOT] com
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Dr. John Jose works in the domain of multicore computer architecture. His research group in Multicore ARchitecture and Systems (MARS) Lab explore problems in the following domain.
For more details about ongoing research click here.
  • Network on Chip (NoC) and Cache Optimisation in Tiled Chip Multi-Processors (TCMP)
  • Wireless On Chip Interconnects and Edge/Fog Computing
  • Machine Learning based Domain Specific Accelerators for NoCs
  • Non-Volatile Memory (NVM) Technology
  • Secure System on Chip Design Techniques
  • Disaggregated Memory Management in Data Center Architectures
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Academic Profile
Ph.D Indian Institute of Technology Madras, Chennai, Tamil Nadu 2009-2014
M.Tech Vellore Institute of Technology, Vellore, Tamil Nadu 2004-2006
B.Tech College of Engineering Adoor, Cochin University, Kerala 1999-2003

Professional Experience
Assistant Professor, CSE Department, IIT Guwahati, Guwahati. 2015 till date
Assistant Professor, Rajagiri School of Engineering & Technology, Cochin. 2013 to 2015
Visiting Faculty, IIITDM , Kancheepuram. 2013 (6 months)
Teaching & Research Assistant, CSE Department, IIT Madras, Chennai. 2009 to 2013
Assistant Professor, Viswajyothi College of Engineering and Technology, Muvattupuzha. 2003 to 2008
News Highlights [Last updated on 24.07.2021]
  • 24.07.2021: Paper titled Packet Header Attack by Hardware Trojan in NoC based TCMP and its Impact Analysis by Vedika J. Kulkarni et al. is accepted for publication in 15th IEEE/ACM International Symposium on Networks-on-Chip [NOCS-2021].
  • 23.07.2021: Dipika Deb submitted her Ph.D thesis titled Performance Enhancement of Tiled Multicore Processors using Prefetching and NoC Packet Compression.
  • 19.07.2021: Abhijit Das joined AMD Bangalore as Silicon Design Engineer.
  • 01.07.2021: Abhijit Das submitted his Ph.D thesis titled Designing Data-Aware Network on Chip for Performance.
  • 09.06.2021: Paper titled Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems by Abhijit Das et al. is accepted for publication in IEEE Transactions on Very Large Scale Integration Systems..
  • 07.06.2021: Paper titled FlitZip: Effective Packet Compression for NoC in MultiProcessor System-on-Chip by Dipika Deb et al. is accepted for publication in IEEE Transactions on Parallel and Distributed Systems..
  • 15.05.2021: Springer book chapter titled Dynamic Shielding and Trojan-aware NoC Routing by Manju R. et al. is available online.
  • 11.04.2021: Paper titled Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning by Sivakumar S. et al. is accepted for publication in Great Lakes Symposium on VLSI..
  • 07.04.2021: John Jose receives 2021 Qualcomm Faculty Award with a gift funding of US$ 15,000.
  • 21.03.2021: Paper titled Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty by Abhijit Das et al. is accepted for publication in IEEE Transactions on Computers.
  • 20.02.2021: Paper titled Revising NoC in Future Multi-Core based Consumer Electronics for Performance by Abhijit Das et al. is accepted for publication in IEEE Consumer Electronics Magazine.