JOHN JOSE

Assistant Professor
Department of Computer Science & Engineering
Indian Institute of Technology Guwahati
Guwahati - 781039, Assam, India

Contact Details

Office: Room Number H-201, CSE Dept, IITG
Phone: 0361- 2583256
Email: johnjose [AT] iitg [DOT] ac [DOT] in
             johnjose004 [AT] gmail [DOT] com
Home   |   Research   |   Courses   |   Students   |   External Talks

Regular fulltime Ph.D scholar vacancies with institute scholarship available in my research group. If anyone is interested in my research domain listed below, you may contact me in email with a detailed CV. Refer to Our admissions page for more details.
NPTEL MOOCs Youtube links    ||    Advanced Computer Architecture    ||    Multi-Core Computer Architecture - Storage and Interconnects


Dr. John Jose works in the domain of multicore computer architecture. His research group in Multicore ARchitecture and Systems (MARS) Lab explore problems in the following domain. For more details about ongoing research click here.
  • Network on Chip (NoC) and Cache Optimisation in Tiled Chip Multi-Processors (TCMP)
  • Wireless On Chip Interconnects and Edge/Fog Computing
  • Machine Learning based accelerators for NoCs
  • Non-Volatile Memory (NVM) Technology
  • Secure System on Chip Design Techniques
  • Disaggregated Memory Management in Data Center Architectures
|| * DBLP * || * Google Scholar * || * Scopus Author Profile * || * IRINS Faculty Profile * ||

Academic Profile
Ph.D Indian Institute of Technology Madras, Chennai, Tamil Nadu 2009-2014
M.Tech Vellore Institute of Technology, Vellore, Tamil Nadu 2004-2006
B.Tech College of Engineering Adoor, Cochin University, Kerala 1999-2003

Professional Experience
Assistant Professor, CSE Department, IIT Guwahati, Guwahati. 2015 till date
Assistant Professor, Rajagiri School of Engineering & Technology, Cochin. 2013 to 2015
Visiting Faculty, Indian Institute of Information Technology Design and Manufacturing (IIITDM), Kancheepuram. 2013 (6 months)
Teaching & Research Assistant, CSE Department, IIT Madras, Chennai. 2009 to 2013
Lecturer, Assistant Professor, Viswajyothi College of Engineering and Technology, Muvattupuzha. 2003 to 2008
News Highlights

11.04.2021: Paper titled Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning by Sivakumar S. et al. is accepted for publication in Great Lakes Symposium on VLSI [GLSVLSI-2021].

07.04.2021: Dr. John Jose has been named as a recipient of 2021 Qualcomm Faculty Award with a gift funding of US$ 15,000.

21.03.2021: Paper titled Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty by Abhijit Das et al. is accepted for publication in IEEE Transactions on Computers.

01.03.2021: Paper titled Traffic aware routing in 3D NoC using interleaved asymmetric edge routers by Rose G. Kunthara et al. is published in Elsevier Nano Communication Networks.

20.02.2021: Paper titled Revising NoC in Future Multi-Core based Consumer Electronics for Performance by Abhijit Das et al. is accepted for publication in IEEE Consumer Electronics Magazine.

15.02.2021: Book chapter titled Dynamic Shielding and Trojan-aware NoC Routing by Manju R. et al. is included in the book Network-on-Chip Security and Privacy [Springer].

05.01.2021: Paper titled COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC based MPSoCs by Dipika Deb et al. is published in ACM Transactions on Design Automation of Electronic Systems .

22.09.2020: Abhishek Kumar received the best thesis award from M.Tech-CSE (2019-20 batch) in the 22nd Convocation of IITG for the thesis titled Exploiting NoC Buffers as Victim Cache between Last Level Cache and Main Memory.


Last updated on 27.04.2021.