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The System Simulation Laboratory is a fully computerized laboratory equipped with highly configured PCs and various computational and simulation software like Matlab 2019A and 2020B, Borland C++, FPGA Advantage from Mentor Graphics, Xilinx Design tools Vivado, Cadence Design system, Zeland’s IE3D EM simulation SW, Altera’s Quartus webpack, Electronics Workbench, MicroSim Design Lab (EDA software), Cadstar PCB Design, Elanix’s Systemview, HP-Eesof, Hypersignal and Operating System such as Redhat Enterprise Linux, Microsoft windows 10, Ubuntu etc.
EE311 Introduction to VLSI: Design of inverter & Extraction, Design of NAND & Extraction, Design of NOR, Design of T & D FF, Design of MUX, Design of 2 Bit Full ADDER, Design of 4Bit Multiplier, Modeling, Simulation & Extraction run ELDO, Design of cells for UWB base band processor, Design of SRAM Cell & Simulation.
EE528 Signals and Systems Simulation: Introduction to OCTAVE and C Programming, Implementation of different mathematical operators and functions in OCTAVE/C, 1D/2D Signal generation, operations and display in OCTAVE/C, Verification of system properties in OCTAVE / C, Study of Fourier analysis of signals in OCTAVE / C, Study of Laplace transform and z-transform in OCTAVE / C, Study of sampling in time &frequency domain, DFT and FFT in OCATVE / C, Implementation of structures of digital signal processing systems in OCTAVE /C, Design of digital FIR filters in OCTAVE/C, Design of digital IIR filters in OCTAVE/C, Decimation, interpolation and fractional sampling rate conversion in OCTAVE / C, Analysis and Synthesis of Non-stationary signals in OCTAVE / C. Feature extraction from non-stationary signals in OCTAVE / C14.Pattern modeling from non-stationary signals in OCTAVE / C.
EE513 VLSI Lab I: Parameter extraction for NMOS and PMOS devices, Analysis of Inverter characteristics for arbitrary sizing, Designing of CMOS inverter for a given specifications, Introduction to layout techniques and implementation of inverter in layout, Analysis and designing of NAND logic gate along with the layout. Introduction to progressive sizing and also designing of inverter chains using progressive sizing to improve delay performance, Extraction of integrated resistance and capacitor's parameters8.Designing of integrated resistor and capacitor for the required values.
EE517 VLSI Lab II: Realization of Common Source Amplifier, Analysis and designing of basic amplifiers such as CS, CG and CD stages, Characterization of Current Mirrors, Analysis and designing of Cascode amplifiers, Analysis and designing of Differential Amplifiers, Analysis and designing of OTAs, Analysis and designing of different Feedback Topologies, Analysis and designing of Single, Two and Three stage Opamps, Analysis and designing of Bandgap References, Analysisand designing of Power Amplifiers.
EE518 VLSI Lab III: Introduction to Verilog Design and Small Design Implementations to understand Verilog and EDA tools required for the lab, Design of 8-Bit Adder, 32-Bit Adder and Multiplier, Single-Cycle MIPS Datapath, Single-Cycle MIPS Control, Single-Cycle MIPS Branches, 5-Stage MIPS Processor (Pipelining), Adding a Simple Branch Predictor to MIPS Processor, Implementing Full Forwarding to MIPS ProcessorLab Project.
EE558 Applied Controls Laboratory: Compensator design using root locus and state feedback, Stability and controllability analysis, Analysis and design using frequency response techniques, Real time applications of control system concepts, Simulation of linear and nonlinear systems; Observer design, System Modeling, OrderReduction and Controller Design.
EE538 Communication System Lab: Introduction to Matlab, Random Variables and Plot, Scatter Plot, Signal Constellations, Noise, Bit Error Probability in AWGN, Introduction to Simulink, BER in AWGN, Signal Trajectory, Eye Diagram and Power Spectral Density, BER of Hamming (7,4) Code, Introduction to ns-2, BER of Convolutional Codes, Data CompressionBER in Fading Channels.
Junior Technical Superintendent