MARS Research Seminar Series

Name	Topic	Date
Sivakumar S	Prefetch-Aware DRAM Controller	10-03-2017
Abhijit Das	Application-Aware Prioritization Mechanisms for On-Chip Networks	22-02-2017
Reshma Raj R S	Managing Hotspot in NoC by cost-effective Deflection Routing	08-02-2017
Aswathy N S	Cost-effective Throttling Technique in NoC	08-02-2017
Dipika Deb	Efficient computation in CNN	29-08-2017
Manjari Saha	Paradigm shift in Network-on-chip to achieve scalability	05-09-2017
Sibarpit Chandan	Balanced pre-fetching Aggressiveness controller for NOC based Multiprocessor	12-09-2017
Abhijeet Das	A case for MLP-Aware cache Replacement	20-09-2017
Annesha Baruah	Design and implementation of an NOC virtual channel router	03-10-2017
Sivakumar S.	A survey of technique for Architecting DRAM caches	--
Manjoni Saha	Energy Efficiency in WNoc	21-11-2017
Ananda Y R	Tiered latency DRAM: A low latency and low cost DRAM architecture	03-01-2018
Ananda Y R	Improving DRAM performance in 3-D ICs via temperature aware refresh	24-01-2018
Sivakumar S.	Non-Volatile processors	01-02-2018
Midhula K.S.	Minimally buffered single cycle deflection routers in NoC	15-02-2018
Manju B. Menon	Performance improvement in multicore processors by prefetch friendly on chip interconnects	22-02-2018
Manju R.	JENGA: solftware defined cache heirarchies	08-02-2018
Shashank S.kudler & Rohith M.K.	---------	09-04-2018
Sarath Babu	Application-Aware rounting in Network-on-Chip	09-04-2018
Jyoti Prakash & S. Manishankar	Effective utilization of resources in TCMP using for core prefecting	18-06-2018