Chandan Karfa

CS 526: CAD for VLSI

  • 6th March 2018 : Research Paper Presenteation Schedule: 12th March (Monday) 6PM-7:30PM, Venue: CSE Conference Room.

  • 6th March 2018 : Project Presenteation Schedule: 8th March (Thursday) 6PM-7:30PM, Venue: CSE Conference Room.

  • 17th February 2018 : Class Test 1: Tuesday, 20th February 11AM-12PM.

  • 17th February 2018 : Sample input format for projects: Check Project allocation page

  • 12th February 2018 : The XEROX of Chapter 6, 7 and 8 of G. De Micheli's book is kept in core 1 Xerox Center. Please collect your copy.

  • 30th January 2018 : The class of 9th February is rescheduled to 8th February 8AM-9AM slot.

  • 30th January 2018 : Rajesh D. (Email: will teach Verilog on 5th aand 6th February 2018. VENUE: CSE SEMINAR ROOM (GROUND FLOOR)

  • 27th January 2018 : PROJECT Allocation. We will meet on Tuesday (30th January) from 6Pm -7PM at CSE Conference room to discuss the projects in detail.

  • 12th January 2018 : The XEROX of G. De Micheli's book is kept in core 1 xerox center. Please collect your copy.

  • 12th January 2018 : No class on 16th January. Next class is on Friday (19th January)

  • 3rd January 2018: Class will start from 8th January 2018 (10AM, Room No: 2204, Core 2)

  • 3rd January 2018: For any email regarding CS526 to me, Subject of the email MUST starts with CS526, i.e. the subject pattern would be like “CS526: <your issue>”.

Class Timing and Venue:

  • Monday: 10AM-11:55AM, Thuesday: 11AM-11:55AM, Friday: 9AM-10:55AM

  • Venue: 2204, Core 2


  • Introduction to CAD for VLSI

  • High-level Synthesis: Scheduling, Allocation and Binding, Data path and Controller Generation, Impact of compiler optimizations on Synthesis results, Coding style.

  • Logic Synthesis: Two level commbinational logic optimizations, multiple-level combinational logic optimizations, Sequential logic optimizations.

  • Physical Synthesis: Floorplanning, Placements, Routing algorithms.

  • FPGA Synthesis: FPGA basics, LUT Mapping, RAM and DSP inferences.

  • RTL Optimizations for area, power and timming: Retiming, folding, pipelining, register balancing, clock gating.

  • Verilog

Text Books:

  • [Mitcheli] G. De Micheli. Synthesis and optimization of digital circuits, India Edition, 2003.

  • [Sherwani] N. A. Sherwani, Algorithms for VLSI Physical Design Automation, Bsp Books Pvt. Ltd., 3rd edition, 2005.

  • [Kilts] Steve Kilts, Advanced FPGA Design, Wiley, 2007.

  • [Gajski] D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992.

  • [Parhi] K. Parhi: VLSI Digital Signal Processing Systems: Design and Implementation, Jan 1999, Wiley.

  • Research papers (soft copies will be provided).


  • Sanjit Kumar Roy (

  • Pavan Ganesh JeeReddy (

Grade Calculation

Surprize Quizzes 10%
Reseach Paper Studies / Projects 20%
MidSem 30%
End Sem 40%


Sl No Date Topic Resources
1 8th January 2018 Introduction
2 9th January 2018 High-level Synthesis flow with an example Similar lecture in youtube
3. 12th January 2018 High-Level Synthesis: Scheduling Problem Formulation Mitcheli: Ch 5
15th January 2018 Holiday
16th January 2018 No Class
4. 19th January 2018 ASAP and ALAP Scheduling, Mobility Mitcheli: Ch 5
5. 22nd January 2018 ILP formulation of ML-RC and MR-LC Scheduling Mitcheli: Ch 5
6. 23rd January 2018 Multiprocessor Scheduling: HU's algorithm Mitcheli: Ch 5
7. 25th January 2018 Heuristic-based Scheduling: List Scheduling Mitcheli: Ch 5
8. 29th January 2018 FU Allocation and Binding: Problem formulation Mitcheli: Ch 6
9. 30th January 2018 Fu allocation and binding for non-hierarchical graphs, left-edge algorithm Mitcheli: Ch 6, Ch 2
2nd February 2018 No Class: Alcheringa Mitcheli: Ch 6
10. 5th February 2018 Verilog ppt1
11. 6th February 2018 Verilog ppt2, ppt3
12. 8th February 2018 FU allocation and binding for hierarchical graphs, Register allocation and Bind Micheli: Ch 6
13. 12th February 2018 Register allocation and Bind, Port Assignment Problem Micheli: Ch 6
14. 13th February 2018 Port Assignment Problem, Data path Synthesis Follow Class notes
15. 16th February 2018 Data path Optimizations and Controller Synthesis Scanned Copy from Gajski's book
16. 17th February 2018 Impact of Coding Style on HLS Results Vivado User Manual: Chapter 3
17. 19th February 2018 Impact of Coding Style on HLS Results
18. 20th February 2018 Impact of Compiler Optimizations on HLS results, Class Test 1 Mitcheli: Ch 3.4, Paper1
19. 23th February 2018 Impact of Compiler Optimizations on HLS results Paper2, Paper3, Paper4
28th February 2018 Mid Sem Examination (9AM-12PM)
20. 5th March 2018 Retiming Parhi: Ch 4
21. 6th March 2018 Retiming Parhi: Ch 4
22. 12th March 2018 RTL optimization for Speed Kilts: Ch 1
23. 13th March 2018 RTL optimization for Speed Kilts: Ch 1
24. 16th March 2018 RTL optimization for Area Kilts: Ch 2
25. 19th March 2018 RTL optimization for Power Kilts: Ch 3, Ch 6
26. 20th March 2018 RTL optimization for Power
27. 22nd March 2018 BDD
28. 23rd March 2018 Logic Synthesis