January 2021-

Area: Design Autiomation and Verificaton of Masking

Email: s.nilotpola@iitg.ac.in

July 2022-

Area: Logic Locking

Email: pkarmakar@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2022-

Area: ML for Logic Synthesis

Email: akash@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2023-

Area: ML/LLM for EDA

Email: m.bhabesh@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2023-

Area: Acclerator Design and Security Analysis of ML

Email: r.eddula@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2024-

Area: ML for Physical Synthesis

Email: innocent@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2025-

Area: Formal Verification

Email: nishantk@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2026-

Area: ML Security

Email: anadig@iitg.ac.in

July 2026-

Area: EDA for Security

Email: monalisharoy@iitg.ac.in

(Joint supervision with Dr. Bernard Nongpoh)

July 2026-

Area: ML for EDA

Email: dipayankar@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

July 2017 – November 2023

Area: Security Verification of Compiler Optimizations: An Information Flow Perspective

Email: priya176101006@iitg.ac.in

Next Position: Assistant Professor, IIT Dhanbad

July 2017 – June 2023

Thesis: Efficient Techniques for Scheduling DAG Applications in Distributed Environments

Email: debab176101003@iitg.ac.in

Next Position: Assistant Professor, SRM University

(Joint supervision with Dr. Arnab Sarkar)

January 2018 – October 2022

Thesis: Reverse-Engineering of High-level Synthesis and Its Applications

Email: ma.adem@iitg.ac.in

Next Position: Faculty at Defence Engineering College, Ethiopia

August 2016 – May 2022

Thesis: Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms

Email: d.surajit@iitg.ac.in

Next Position: Assistant Professor, National Forensic Sciences University, Delhi

(Joint supervision with Dr. Santosh Biswas)

August 2016 – August 2020

Thesis: Formal Verification and Security Analysis of High-level Synthesis

Email: r.chouksey@iitg.ac.in

Next Position: Lead Engineer at Cadence

2025 – 2027

Thesis: LLM for Formal Verification

2025 – 2027

Thesis: EDA for Hardware Security

2025 – 2027

Thesis: ML for EDA

2025 – 2027

Thesis: ML Accelarator

2023 – 2027

Thesis: GPU Accelerated Gate Sizing (Differentiable Gate Sizing)

2023 – 2027

Thesis: Security Aware EDA - Clock Tree Synthesis

2023 – 2027

Thesis: Gate Resizing - Naman's Extension

2023 – 2027

Thesis: Security Aware EDA - Placement

2023 – 2027

Thesis: AlphaEvolve for Placement/Routing

2023 – 2027

Thesis: Design Intent EDA

2023 – 2027

Thesis: ABC (LEAP + Super Gate Merging)

2023 – 2027

Thesis: Core LLM Knowledge Editing for Hardware Design Tasks

2023 – 2027

Thesis: Formal Verification of LLM-Based Code Generation

2023 – 2027

Thesis:

2023 – 2027

Thesis:

2023 – 2027

Thesis:

2024 – 2026

Thesis: Hardware Accelerator for Hybrid Transformer-based Underwater Object Detection

2024 – 2026

Thesis: A Reinforcement Learning Guided Scheduling in High-Level Synthesis

2024 – 2026

Thesis: Design Space Exploration of Gadget-Based Masked Cryptographic Hardware

2024 – 2026

Thesis: Physical Aware Logic Restructuring for Timing Improvement

2024 – 2026

Thesis: MCTS-based Logic Restructuring for Timing Closure in Physical Synthesis

2024 – 2026

Thesis: Machine Learning Guided Technology Mapping in the ABC Logic Synthesis Framework

2023 – 2025

Thesis: Protecting ML models from Physical Side Channel Attacks via Masking

2023 – 2025

Thesis: Power Side-Channel Secure Register Transfer Level Design using Ad-hoc Techniques

2023 – 2025

Thesis: BDD Based Attack on Logic Locking

2023 – 2025

Thesis: RTL Information Leakage Analysis and its Application in Analysis of High-level Synthesis Security

2023 – 2025

Thesis: Design Space Exploration of Gadget-based Masked Hardware

2023 – 2025

Thesis: Efficient High-Level Synthesis of Post Quantum Cryptography Algorithms

2022 – 2024

Thesis: Formal Verification of PSCA Security of High Level Synthesis Generated Cryptographic Design

2022 – 2024

Thesis: Power Side-Channel Secure Register Transfer Level Design

2022 – 2024

Thesis: Exploring Advanced Verification Techniques: From Security Verification of LLVM, Hardware Fuzzing and Automated Assertion Generation

2022 – 2024

Thesis: An SMT based Model Extraction Attack on Neural Networks

2022 – 2024

Thesis: An Oracle Guided Attack on State Space Obfuscation Technique

2021 – 2024

Thesis: Statistical Attack on Logic Locked Designs with Dishonest Oracle

2021 – 2023

Thesis: Logic Locking: Analysing the Area and Latency Overhead of Locked Designs

2021 – 2023

Thesis: C to RTL Equivalence Checking

2021 – 2023

Thesis: Scalable SMT Attack on Higher Level Locking

2021 – 2023

Thesis: Predicting Robustness of Logic Locking

2020 – 2023

Thesis: Attacks on locked Combinational and Sequential circuits

2020 – 2022

Thesis: Verification of Dataflow Optimization in Array-Intensive Programs

2020 – 2022

Thesis: Information Leakage Analysis of Compiler Optimizations

2020 – 2022

Broad Area: Logic Encryption at Higher Abstraction Level

2019 – 2021

Thesis: Hardware Trojan Detection in High-level Synthesis Generated RTLs

2019 – 2021

Thesis: An RTL-to-C Reverse Engineering based Fast Simulation Framework for High-level Synthesis

2019 – 2021

Thesis: A Statistical Approach to Measure Robustness of Gate-Level Logic Locking

2019 – 2021

Thesis: Genetic Algorithm based Attack on Register Transfer Level Locking

2018 – 2020

Thesis: A Fast Simulation Framework for High-level Synthesis

2018 – 2020

Thesis: Register Transfer Level Logic Obfuscation

2017 – 2019

Thesis: Property Verification in Business Process Models embedded with SBVR-based Business Rules

2017 – 2019

Thesis: Formal Verification of Testability Transformations

2017 – 2019

Thesis: Deadlock and Livelock Detection in NoC using Generic Communicating Finite State Machine

(Joint supervision with Dr. Santosh Biswas)

2017 – 2017

Thesis: Register Manipulation using Automatic Register Balancing

(Joint supervision with Dr. Santosh Biswas)

2016 – 2018

Thesis: Inverse Operation Detection and Counter Example Generation during Path Based Equivalence Checking

2016 – 2018

Thesis: NoC Verification: Deadlock Detection Using Bottom Up Approach

(Joint supervision with Dr. Santosh Biswas)

2016 – 2018

Thesis: A Top-Down Approach for Deadlock Detection in NoC Using Communicating Finite State Machine

(Joint supervision with Dr. Santosh Biswas)

2022 – 2026

Thesis: ML for Logic Synthesis

2022 – 2026

Area: RTL Power Prediction

2022 – 2026

Thesis: Biochip (guided by Dr. Sukanta)

2022 – 2026

Thesis: Physical Aware Logic Syntesis

2022 – 2026

Area: Netlist to RTL Reverse Engineering

2022 – 2026

Thesis: LLM for EDA

2022 – 2026

Thesis: RL for Scheduling in HLS

2022 – 2026

Thesis: LLM for EDA

2022 – 2026

Thesis: LLM based Verification Assertion Generation

2022 – 2026

Thesis: Biochip (guided by Dr. Sukanta)

2022 – 2026

Thesis: Physical Aware Logic Syntesis

2021 – 2025

Thesis: ML for EDA

2021 – 2025

Area: Attack on Sequential Logic Locking

2021 – 2025

Thesis: ML for Logic Locking

2021 – 2025

Thesis: ML based Simulation Acceleration

2021 – 2025

Thesis: Logic Synthesis

2021 – 2025

Area: ML for EDA

2021 – 2025

Thesis: ML for EDA

2021 – 2025

Thesis: EDA

2021 – 2025

Thesis: Logic Synthesis

2021 – 2025

Thesis: Security Verification

2021 – 2025

Thesis: Security Verification

2020 – 2024

Thesis: Protection Against Scan-Chain-Based Model Extraction Attacks (Jointly with Dhruv)

2020 – 2024

Area: Security of ML Model

2020 – 2024

Thesis: Power Side Channel Secure RTL Design

2020 – 2024

Thesis: ML Guided Cut Choices for ASIC Technology Mapping (Jointly with Harsh)

2020 – 2024

Area: ML for EDA

2020 – 2024

Thesis: Attacks on Combinational and EFPGA Logic Locking (Jointly with Kartik)

2020 – 2024

Area: Logic Locking

2020 – 2024

Thesis: Identifying Information Leakage in RTL Design

2020 – 2024

Thesis: Speedup of RTL Simulation Using Machine Learning Techniques

2019 – 2023

Thesis: Counter Example Generation for Insecure Transformation of Compiler Optimizations

2019 – 2023

Thesis: Power Side Channel Secure RTL Design

2019 – 2023

Thesis: Scalable Attack on Combinational Circuits

2019 – 2023

Thesis: High Level Synthesis and Optimization of ML Models

2019 – 2023

Thesis: Translation Validation of High Level Synthesis

2019 – 2023

Thesis: SAT Based Attacks on Machine Learning Models

2019 – 2023

Thesis: Predicting Outputs of RTL Circuits Using Machine Learning

2018 – 2022

Thesis: Formal Verification of Security Countermeasures Against Power Side-Channel Attacks

2018 – 2022

Thesis: Security-Aware DAG Scheduler for Heterogeneous Distributed Systems

2018 – 2022

Thesis: Hardware Security against IP Theft

2018 – 2022

Thesis: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems

2018 – 2022

Thesis: Security Analysis of C/C++ Programs

2018 – 2022

Broad Area: Formal Verification Of Security Measures Against Timing Side-Channel Attacks

2017 – 2021

Broad Area: Hardware Trojan Detection in Post-silicon Validation

2017 – 2021

Broad Area: Analysis of Information Leakage in LLVM Compiler

2017 – 2021

Broad Area: Data-driven Equivalence Checking

2017 – 2021

Broad Area: Logic Locking

2017 – 2021

Broad Area: Compiler Security

2016 – 2020

Broad Area: Logic Locking

2016 – 2020

Broad Area: Hardware Trojan Detection

2016 – 2020

Broad Area: Equivalence Checking of Programs

2016 – 2020

Broad Area: HLS Obfuscation

2015 – 2019

Broad Area: Verification of Deep Neural Networks

2015 – 2019

Broad Area: Verification of Deep Neural Networks

2015 – 2019

Broad Area: Deep Steganography

2015 – 2019

Broad Area: Verification of Database Driven Applications

2014 – 2018

Broad Area: Bottom-up Equivalence Checking

2014 – 2018

Broad Area: High-level Synthesis

2014 – 2018

Broad Area: High-level Synthesis

2014 – 2018

Broad Area: Type systems and secure compilation of WebAssembly

2014 – 2018

Broad Area: Loop Invariant Generation

2013 – 2017

Area: Program Equivalence using CVC4

2013 – 2017

Area: Program Equivalence using CVC4 (Joint project with Ravi Kumar)

2013 – 2017

Area: Verification of Testability Transformations

2013 – 2017

Area: Design and Development of a Material Selection Software