20th International Symposium on VLSI Design and Test


May 24th- May 27th 2016, Guwahati, India

Poster Presentation
Day 1(25 May) Poster Session-I (Digital & System Design)
84Formal Verification of Switched Capacitor DC to DC Power Converter Using SPICE Circuit Simulation Traces
91Reducing FIFO Buffer Power Using Architectural Alternatives at RTL
90FFT/IFFT implementation using Vivado HLS
126A Low Power High Speed Hybrid Full Adder
172Energy-efficient Reconfigurable Framework for Evaluating Hybrid NoCs
106Low-Cost Fault-Tolerant Design of QCA XOR Gates
89Golden IC free Methodology for Hardware Trojan Detection using Symmetric Path Delays
219Design of Fault Tolerant Majority Voter for TMR Implementation in QCA
79A Strategy for Fault Tolerant Reconfigurable Network-on-Chip Design

Day 2(26 May) Poster Session-II (Analog & RF Design)
130Smart Handheld Platform For Electrochemical Bio Sensors
14Design, Integration and Performance Analysis of Σ∆ ADC for Capacitive Sensor Interfacing
145FSK Demodulator And FPGA Based BER Measurement System For Low IF Receivers
8A High CMRR, High Resolution bio-ASIC for ECG Signals
11Temperature Dependent IR-Drop and Delay Analysis in Side-Contact Multilayer Graphene Nanoribbon Based Power Interconnects
111Data Dependent Suprious Power Reduction for FWM
200A Novel Low power 6-bit FLASH ADC using Charge steering amplifier For RF Application
114A Mismatch Insensitive Reconfigurable Discrete Time Biosignal Conditioning Circuit in 180 nm MM CMOS Technology
191An 8-bit 500 MSPS Segmented Current Steering DAC using Chinese Abacus Technique
119Quantification of figures of merit of 7T and 8T SRAM cell in sub-threshold region and their comparison with the conventional 6T SRAM cell