Call For Papers

Researchers, academicians and professionals are invited to submit paper in the topic of interest (but not limited to)

VLSI Design and Semiconductor Device Modeling : Analog and RF mixed signal design; Design and modeling of digital circuits and systems; FPGA prototyping of algorithms; Synthesis; Optoelectronic devices and circuits; MEMS, Deep Submicron and Nanometer devices and circuits; Power analysis and low-power design; Thermal analysis and temperature aware design; Physical design, packaging and board design; CAD for design and technology; High performance computing; System-on-chip designs; Networks-on-chip Design .

Emerging Technology: Nanoscale computing and nanotechnology; Reversible computation; Nano-Electro-Mechanical Systems (NEMS); CAD research in the areas of emerging technology and emerging systems.

Testing and Verification: Design for testability; Test generation and fault simulation; Built-in self- test; Verification (simulation and formal); Design for manufacturability and yield analysis; Testing memories and regular logic arrays.]

Embedded Systems: Hardware/software co-design and verification; Audio, Image and Video processing; Reconfigurable systems; Applications in communications, Encryption, Security, Compression, etc.; Embedded software tools; FPGA prototyping of complete systems; CAD for embedded systems.

Soft copies of papers should be submitted as a .pdf file as per the IEEE conference paper format submits not exceeding six A4 size pages. And soft copy of the paper should be uploaded on the symposium web site. There will be double blind review of the paper. Therefore do not include authors’ name in submitted paper. A Paper with authors’ names will not be considered for review. The paper must include an abstract of about 250 words and maximum of five keywords related to the topic of the paper.

Authors of the accepted papers will be informed by email. Information about necessary revisions will be communicated to the corresponding author through email. The author(s) will have to incorporate the suggestions and will have to send the revised camera ready copy of the paper in the given time limit.

Along with the paper, authors are required to submit an undertaking form stating that, the paper has not been published previously, is not under consideration for publication elsewhere, and if accepted will not be published elsewhere in the same form.

It is mandatory for atleast one of the authors to register in non-student category for publication of the paper in proceedings. For the author presenting more than one papers, it is mandatory to register and present each paper separately.

The paper accepted for oral presentation will be recommended to IEEE Conference Publication Program (CPP) to include it on the IEEExplore website provided the following conditions are fulfilled: (a) it strictly complies with IEEE conference paper formatting guidelines, (c) the paper is presented in the conference by at least one of the registered authors and (d) the filled and signed copy-right transfer form is submitted along with the paper.

Tutorial: We also invite to submit proposal for full or half day tutorials to be presented at VDAT 2016.

Work-in-progress (WIP) Forum: Research students can submit their WIP and present their work at VDAT 2016.

Fellowship: There are some fellowships (Travel & Registration grant) available and for that one need to apply at symposium website before deadline.


Prof. Sukumar Nandi
General Co-chair
VLSI Design and Test Symposium (VDAT-2016),
Department of Computer Science & Engineering,
Indian Institute of Technology Guwahati,
Phone: +91 361 2582400


Last Date for Abstract Submission:January 31, 2016 (IST)
Last Date for Paper Submission:February 3, 2016 (IST)
Notification of Acceptance for Papers: April 10, 2016
Last Date for Tutorial Proposal: January 31, 2016

Fellowship Application Deadline: May 12, 2016
Authors Registration Deadline: May 15, 2016

Department of CSE & EEE, Indian Institute of Technology Guwahati, Assam, Pin-781039
Email:, Phone: +91 361 2582400