BM Bhabesh Mali
Artificial Intelligence for Chip Design

Bhabesh
Mali

PhD Scholar · Department of Computer Science and Engineering · IIT Guwahati

I work on AI for chip design, focusing on machine learning for electronic design automation, particularly high-level synthesis and logic synthesis, as well as LLM-assisted design verification.

View Resume Selected Publications Email Me
ResearchMachine Learning for Electronic Design Automation, LLM-assisted Design Verification
LabAutomation, Verification and Systems (AVS)
AdvisorsDr. Chandan Karfa and Dr. Sukanta Bhattacharjee
AI for Chip Design
EDA + ML
LLM-assisted Design Verification
Research

Research Themes

My work connects AI models with core chip-design stages including synthesis, mapping, scheduling, verification, and quality evaluation.

Theme 01

LLM-Assisted Design Verification

Generating and refining SystemVerilog assertions from natural-language specifications and RTL, taking assitance of LLMs/SLMs.

Theme 02

Machine-Learning-Based High-Level Synthesis

Applying machine learning to operation scheduling, resource allocation, and design-space exploration under latency and resource constraints.

Theme 03

Machine-Learning-Based Logic Synthesis

Using learned models to guide logic optimization and technology mapping to reduce computation runtime and provide quality-of-results improvement.

AI-for-Chip-Design Pipeline

AI for Chip design simply means the development of intelligent EDA workflows in which chip-design problems are represented in machine-understandable forms and addressed using AI-guided reasoning.

  • An end-to-end AI-guided flow from C/C++ code to RTL, a gate-level netlist, and final chip implementation
  • Prediction and generation using machine learning, reinforcement learning, GNNs, and LLMs in the flow
  • Tool-driven validation using synthesis and formal-verification frameworks
Current Work

Research Projects

Selected ongoing and recent projects that shape my doctoral research in AI for chip design and adjacent intelligent systems.

EDA · Mapping

FedTM

Federated ASIC technology mapping uses FL-based learned models for cut classification and delay prediction across heterogeneous clients and technology libraries.

FedTM Server FedAvg aggregation Client 1 Local cuts + library Classifier Predictor Client 2 Local cuts + library Classifier Predictor Client 3 Local cuts + library Classifier Predictor Client 4 Local cuts + library Classifier Predictor Global models used in the mapping flow
Verification · LLM

SANGAM / ChIRAAG

LLM-assisted SystemVerilog assertion generation using iterative refinement frameworks, formal validation of generated SVA, and quality-aware evaluation.

HLS · RL

Graph-based Scheduling

Graph neural network policies and reinforcement learning for operation scheduling, resource allocation, and latency-constrained high-level synthesis.

Scholarship

Selected Publications

Publications across EDA, design verification, federated learning, healthcare AI, and intelligent distributed systems.

FedTM: Federated ASIC Technology Mapping

Bhabesh Mali, Akash Lal Dutta, Chandrabhushan R. Chigarapally, Chandan Karfa, Sukanta Bhattacharjee · ACM TODAES

SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine

Adarsh Gupta, Bhabesh Mali, Chandan Karfa · IEEE ICLAD

ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation

Bhabesh Mali, Karthik Maddala, Vatsal Gupta, Sweeya Reddy, Chandan Karfa, Ramesh Karri · IEEE ISVLSI

LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification

Karthik Maddala, Bhabesh Mali, Chandan Karfa · IEEE ITC India

Edge Computing for Latency-Critical Task Offloading in Industry 5.0

Bhabesh Mali, Abhishek Hazra, Nabajyoti Mazumdar, Mohan Gurusamy · IEEE Sensors Letters

SAFe-Health: Guarding FL-driven Smart Healthcare with Federated Defense Averaging against Data Poisoning

Bhabesh Mali, Pranav Kumar Singh, Nabajyoti Mazumdar · Security and Privacy

Updates

Recent News

Selected academic milestones, presentations, and research highlights.

Presented “LLM Assisted Verification Assertion Generation: Challenges and Future Directions”

Presented at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2026).

SANGAM Accepted at IEEE ICLAD

Research on SystemVerilog assertion generation using Monte Carlo Tree Self-Refine.

Qualcomm Innovation Fellowship India 2024

Selected as a finalist.

Student Fellow at VLSID 2024

Participated in VLSID 2024 as a student fellow.

Contact

Let’s Connect

I welcome research discussions and academic collaborations related to AI for chip design, machine learning for EDA, formal verification, and LLM-assisted hardware-design workflows.

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