List of Publications

Refereed Journal Articles

  1. "Pop-Crypt : Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Non-Volatile Main Memories"
    A. Nath and H. K. Kapoor
    IEEE Transactions on on Very Large Scale Integration (TVLSI), IEEE, 2022.

  2. "ALAMNI: Adaptive LookAside Memory based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time"
    P. Das, S. Sharma and H. K. Kapoor
    IEEE Transactions on Computers (TC), IEEE, 2022.

  3. "CAPMIG: Coherence Aware block Placement and MIGration in Multi-retention STT-RAM Caches"
    S S. Manohar and H. K. Kapoor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE, 2022.

  4. "SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories"
    A. Nath and H. K. Kapoor
    IEEE Transactions on Computers (TC), IEEE, 2021.

  5. "CORIDOR: using COherence and tempoRal localIty to mitigate read Disurbance errOR in STT-RAM caches"
    S. S. Manohar, S. Mittal and H. K. Kapoor
    ACM Transactions on Embedded Computing Systems (TECS), ACM, 2021.
    in Special Issue on Memory and Storage Systems for Embedded and IoT Applications

  6. "nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs"
    P. Das and H. K. Kapoor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE, 2020.

  7. "CLU: A near-memory accelerator exploiting the parallelism in Convolutional Neural Networks"
    P. Das and H. K. Kapoor
    ACM Journal on Emerging Technologies in Computing Systems (JETC), ACM, 2020.

  8. "Improving the Performance of Hybrid Caches using Partitioned Victim Caching"
    S. Agarwal and H. K. Kapoor
    ACM Transactions on Embedded Computing Systems (TECS), ACM, 2020.

  9. "TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler"
    S. Moulik, A. Sarkar and H. K. Kapoor
    Journal of Systems Architecture (JSA), Elsevier, 2020.

  10. "Investigating Frequency Scaling, Non-Volatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon"
    K. Rani and H. K. Kapoor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE, 2020.

  11. "Reuse Distance based Victim Cache for Effective Utilisation of Hybrid Main Memory System"
    A. Nath, S. Agarwal and H. K. Kapoor
    ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, 2020.

  12. "Improving the Lifetime of Non-Volatile Cache by Write Restriction"
    S. Agarwal and H. K. Kapoor
    IEEE Transactions on Computers (TC), IEEE, 2019.

  13. "Dynamic Reconfiguration of embedded-DRAM Caches employing Zero Data Detection based Refresh Optimisation"
    S. S. Manohar and H. K. Kapoor
    Journal of Systems Architecture (JSA), Elsevier, 2019.

  14. "Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects"
    K. Rani and H. K. Kapoor
    IEEE Transactions on Very Large Scale Integration (TVLSI), IEEE, 2019.

  15. "Write-Variation Aware Alternatives to Replace SRAM Buffers with Non-Volatile Buffers in On-Chip Interconnects"
    K. Rani and H. K. Kapoor
    IET Computers & Digital Techniques (IET-CDT), IET, 2019.

  16. "Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design"
    S. Chakraborty and H. K. Kapoor
    ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, 2019.

  17. "Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques"
    S. Agarwal and H. K. Kapoor
    Book Chapter in VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, Springer, Vol. 500, Chapter 3, pp. 46-71, 2019.

  18. "Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches"
    S. Agarwal and H. K. Kapoor
    IEEE Transactions on Very Large Scale Integration (TVLSI), IEEE, 2018.

  19. "Analysing the Role of Last Level Caches in Controlling Chip Temperature"
    S. Chakraborty and H. K. Kapoor
    IEEE Transactions on Sustainable Computing (TSUSC), 3(4):289-305, IEEE, 2018.

  20. "Cost Effective Routing Techniques in 2D Mesh NoC using On-Chip Transmission Lines"
    D. Deb, J. Jose, S. Das and H. K. Kapoor
    Journal of Parallel and Distributed Computing (JPDC), Elsevier, 2018.

  21. "Energy Aware Frame Based Fair Scheduling"
    S. Moulik, A. Sarkar and H. K. Kapoor
    Sustainable Computing: Informatics and Systems (SUSCOM), Elsevier, 2018.

  22. "Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets"
    S. Das and H. K. Kapoor
    IEEE Transaction on Parallel and Distributed Systems (TPDS), 28(8):2229-2243, 2017.

  23. "Performance Linked Dynamic Cache Tuning: A Static Energy Reduction Approach in Tiled CMPs"
    S. Chakraborty and H. K. Kapoor
    Journal of Microprocessors and Microsystems (MICPRO), 52:221-235, Elsevier, 2017.

  24. "A Framework for Block Placement, Migration and Fast Searching in Tiled-DNUCA Architecture"
    S. Das and H. K. Kapoor
    ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016.

  25. "PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog"
    K. L. Man, C-U. Lei, H. K. Kapoor, T. Krilavicius, J. Ma and N. Zhang
    Computing and Informatics, 35(1):143-176, 2016.

  26. "A Discrete Event System Approach to Online Testing of Asynchronous Circuits"
    P. K. Biswal, K. Mishra, S. Biswas and H. K. Kapoor
    Journal of VLSI Design, 2015, Hindawi.

  27. "Victim Retention for Reducing Cache Misses in Tiled Chip Multiprocessors"
    S. Das and H. K. Kapoor
    Journal of Microprocessors and Microsystems (MICPRO), 38(4):263-275, 2014. Elsevier.

  28. "A Security Framework for NoC Using Authenticated Encryption and Session Keys"
    H. K. Kapoor, G. B. Rao, S. Arshi and G. Trivedi
    Journal of Circuits, Systems, and Signal Processing, 32(6):2605-2622, 2013. Springer.

  29. "Design and Formal Verification of a Hierarchical Cache Coherence Protocol
    for NoC based Multiprocessors"
    H. K. Kapoor, P. Kanakala, M. Verma and S. Das
    Journal of Supercomputing, 65(2):771-796, August 2013. Springer.

  30. "A Formal Framework for Interfacing Mixed-Timing Systems"
    S. Das, H. K. Kapoor and P. S. Duggirala
    Integration the VLSI Journal, 46(3):255-264, June 2013. Elsevier.

  31. "Formal Approach for DVS-based Power Management for Multiple Server
    System in Presence of Server Failure and Repair"
    L. Chandnani and H. K. Kapoor
    IEEE Transactions on Industrial Informatics (TII), 9(1):502-513, Feb. 2013.

  32. "Model Checking of Independent Compensating Web-Transactions"
    H. K. Kapoor, S. Das, B. Raju and K. L. Man
    IAENG International Journal of Computer Science - IJCS, 2012.

  33. "Specification and Analysis of NCL Circuits"
    J. Ma, H.K. Kapoor, T. Krilavicius, K.L. Man, et. al
    Engineering Letters, 19(3):215-222, Sep 2011, IAENG

  34. "Handling Multiple Hotspots in Wormhole NoCs"
    H. K. Kapoor, S. Das and B. V. Balakrishna
    Indian Journal of VLSI and Electronic System Design (IJVED)

  35. "Process Algebraic View of Latency-Insensitive Systems"
    H. K. Kapoor
    IEEE Transactions on Computers (TC), 58(7):931-944, July 2009

  36. "Controllable Delay-Insensitive Processes"
    M. B. Josephs and H. K. Kapoor
    Fundamenta Informaticae , 78(1):101-130, 2007, IOS Press

  37. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Fundamenta Informaticae, 70(1-2):21-48, March 2006, IOS Press

  38. "Modelling and Verification of Delay-Insensitive Circuits using CCS and the Concurrency Workbench"
    H. K. Kapoor and M. B. Josephs
    Information Processing Letters, 89(6):293-296, March 2004, Elsevier

Refereed Conference/Workshop Papers

    2022

  1. "Exploiting Successive Identical Words and Differences with Dynamic Bases for Effective Compression in Non-Volatile Memories"
    S. Upadhyay, A. Nath and H. K. Kapoor
    The International Symposium on Low Power Electronics and Design (ISLPED) 2022, ACM.

  2. "SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories"
    N. S. Aswathy, S. Bhavanasih, A. Sarkar and H. K. Kapoor
    The ACM Great Lakes Symposium on VLSI (GLSVLSI) 2022, ACM.

  3. "CoSeP: Compression and Content-based Selection Procedure to improve lifetime of encrypted Non-Volatile Main Memories"
    A. Nath and H. K. Kapoor
    The ACM Great Lakes Symposium on VLSI (GLSVLSI) 2022, ACM.

  4. "Hydra: A near hybrid memory accelerator for CNN inference"
    P. Das, A. Joshi and H. K. Kapoor
    The Design, Automation and Test in Europe Conference (DATE) 2022, IEEE.

  5. 2021

  6. "A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems"
    N. S. Aswathy, H. K. Kapoor and A. Sarkar
    The 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 2021, IEEE.

  7. "DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches"
    M. Baranwal, U. Chugh, S. Dalal, S. Agarwal and H. K. Kapoor
    The 22nd International Symposium on Quality Electronic Design (ISQED) 2021, IEEE.

  8. "SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion"
    A. Nath, M. B. Bhosle and H. K. Kapoor
    The 22nd International Symposium on Quality Electronic Design (ISQED) 2021, IEEE.

  9. 2020

  10. "ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects"
    K. Rani and H. K. Kapoor
    The 57th Design Automation Conference (DAC) 2020, ACM.

  11. "WELCOMF : Wear Leveling Assisted Compression using Frequent Words in Non-Volatile Main Memories"
    A. Nath and H. K. Kapoor
    The International Symposium on Low Power Electronics and Design (ISLPED) 2020, ACM.

  12. "DidaSel: Dirty data based Selection of VC for effective utilization of NVM Buffers in On-Chip Interconnects"
    K. Rani, S. Agarwal and H. K. Kapoor
    The International Symposium on Low Power Electronics and Design (ISLPED) 2020, ACM.

  13. "Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache"
    S. Suman and H. K. Kapoor
    The IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020, IEEE.

  14. "Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors"
    C. Joshi, P. Das, A. Kulkarni and H. K. Kapoor
    The 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM.

  15. 2019

  16. "Lightweight Message Encoding of Power-Gating Controller for On Time Wakeup of Gated Router in Network-on-Chip"
    Neelkamal, S. Yadav. and H. K. Kapoor
    The 9th International Symposium on Embedded Computing & System Design (ISED) 2019, IEEE.

  17. "Enhancing the Lifetime of Non-volatile Caches by Exploiting Module-Wise Write Restriction"
    S. Agarwal and H. K. Kapoor
    The 28th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2019, ACM.

  18. "Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks"
    S. S. Manohar, S. Agarwal and H. K. Kapoor
    The 29th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2019, ACM.

  19. "Late Breaking Results: Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs"
    S. Yadav, V. Laxmi, M. S. Gaur and H. K. Kapoor
    The 56th Design Automation Conference (DAC) 2019, ACM.

  20. "Refresh Optimised embedded-DRAM Caches based on Zero Data Detection"
    S. S. Manohar and H. K. Kapoor
    34th ACM Symposium On Applied Computing (ACM-SAC) 2019, ACM.

  21. "Write Variation Aware Non-Volatile Buffers for On-Chip Interconnects"
    K. Rani and H. K. Kapoor
    32nd International Conference on VLSI Design (VLSID) 2019, IEEE. [Best Paper Candidate]

  22. "Write Variation aware Cache Partitioning for Improved Lifetime in Non-Volatile Caches"
    A. Nath and H. K. Kapoor
    32nd International Conference on VLSI Design (VLSID) 2019, IEEE.

  23. 2018

  24. "Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon"
    K. Rani, S. Agarwal and H. K. Kapoor
    8th International Symposium on Embedded computing and system Design (ISED) 2018, IEEE. [Best Paper Award]

  25. "Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors"
    A. Kulkarni, K. Rani, S. Agarwal, S. P. Mahajan and H. K. Kapoor
    8th International Symposium on Embedded computing and system Design (ISED) 2018, IEEE.

  26. "Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors"
    A. Kulkarni, K. Rani, S. Agarwal, S. P. Mahajan and H. K. Kapoor
    International Symposium on Smart Electronic Systems (iSES) 2018, IEEE.

  27. "Towards Near Data Processing of Compare Operations in 3D-stacked memory"
    P. Das and H. K. Kapoor
    The 28th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, ACM.

  28. "Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors"
    A. Kulkarni, S. Chakraborty, S. P. Mahajan and H. K. Kapoor
    The 28th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, ACM.

  29. "Towards Near Data Processing of Convolutional Neural Networks"
    P. Das, S. Lakhotia, P. Shetty and H. K. Kapoor
    31st International Conference on VLSI Design (VLSID) 2018, IEEE.

  30. "Dynamic Thermal Management by using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors"
    A. V Umdekar, A. Nath, S. Das and H. K. Kapoor
    31st International Conference on VLSI Design (VLSID) 2018, IEEE.

  31. "Fault Tolerance in Network on Chip using Bypass Path establishing Packets"
    P. Sharma, S. Agarwal and H. K. Kapoor
    31st International Conference on VLSI Design (VLSID) 2018, IEEE.

  32. "DPFair Scheduling with Slowdown and Suspension"
    S. Moulik, A. Sarkar and H. K. Kapoor
    31st International Conference on VLSI Design (VLSID) 2018, IEEE.

  33. 2017

  34. "Targeting Inter Set Write Variation to Improve the Lifetime of Non-Volatile Caches using fellow sets"
    S. Agarwal and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2017, IEEE. [Best Paper Award]

  35. "Latency Aware Block Replacement for L1 Caches in Chip MultiProcessors"
    S. Das and H. K. Kapoor
    IEEE Computer Society Annual Symposium on VLSI, (ISVLSI) 2017, IEEE.

  36. "Towards a better lifetime for Non-volatile caches in Chip Multiprocessors"
    S. Agarwal and H. K. Kapoor
    30th International Conference on VLSI Design (VLSID) 2017, IEEE.

  37. "Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors"
    S. Chakraborty and H. K. Kapoor
    30th International Conference on VLSI Design (VLSID) 2017, IEEE.

  38. 2016

  39. "Restricting Writes for Energy-efficient Hybrid Cache in Multi-core Architectures"
    S. Agarwal and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, IEEE.

  40. "Static Energy Reduction by Performance Linked Dynamic Cache Resizing"
    S. Chakraborty and H. K. Kapoor
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2016, IEEE.

  41. "Towards A Dynamic Associativity Enabled Write Prediction Based Hybrid Cache"
    S. Agarwal and H. K. Kapoor
    20th International Symposium on VLSI Design and Test (VDAT), 2016, IEEE Xplore.

  42. "Tag Only Storage for Capacity Optimised Last Level Cache in Chip Multiprocessors"
    S. Das, S. Das and H. K. Kapoor
    20th International Symposium on VLSI Design and Test (VDAT), 2016, IEEE Xplore.

  43. "Static Energy Efficient Cache Reconfiguration for Dynamic NUCA in Tiled CMPs"
    S. Chakraborty, S. Das and H. K. Kapoor
    31st ACM/SIGAPP Symposium On Applied Computing (SAC) 2016, ACM.

  44. "Dynamic Associativity Enabled DNUCA to Improve Block Localisation in Tiled CMPs"
    S. Das and H. K. Kapoor
    31st ACM/SIGAPP Symposium On Applied Computing (SAC) 2016, ACM.

  45. "Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches"
    S. Das and H. K. Kapoor
    29th International Conference on VLSI Design (VLSID) 2016, IEEE.

  46. 2015

  47. "An Efficient Searching Mechanism for Dynamic NUCA in Chip Multiprocessors"
    K. Vanapalli, H. K. Kapoor and S. Das
    19th International Symposium on VLSI Design and Test (VDAT), 2015, IEEE Xplore.

  48. "Power Aware Cache Miss Reduction by Energy Efficient Victim Retention"
    S. Chakraborty, S. Das and H. K. Kapoor
    19th International Symposium on VLSI Design and Test (VDAT), 2015, IEEE Xplore.

  49. "Performance constrained static energy reduction using way-sharing target-banks"
    S. Chakraborty, S. Das and H. K. Kapoor
    17th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM 2015)
    associated with IPDPS,
    2015, IEEE.

  50. "Static energy reduction by performance linked cache capacity management in Tiled CMPs"
    H. K. Kapoor, S. Das and S. Chakraborty
    30th ACM/SIGAPP Symposium On Applied Computing (SAC) 2015, ACM.

  51. "Dynamic Associativity Management using Utility Based Way-Sharing"
    S. Das and H. K. Kapoor
    30th ACM/SIGAPP Symposium On Applied Computing (SAC) 2015, ACM.

  52. "Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs"
    S. Das and H. K. Kapoor
    28th International Conference on VLSI Design (VLSID) 2015, IEEE.

  53. 2014

  54. "An Approach for Multicast Routing in Networks-on-Chip"
    M. LakshmiPrasad, S. Das and H. K. Kapoor
    13th International Conference on Information Technology (ICIT) 2014, IEEE.

  55. "RT-DVS for Power Optimization in Multiprocessor Real-time Systems"
    V. Naik, S. Das and H. K. Kapoor
    13th International Conference on Information Technology (ICIT) 2014, IEEE.

  56. "Modelling and Analysis of Wireless Communication over Networks-on-Chip"
    A. Kumar and H. K. Kapoor
    18th International Symposium on VLSI Design and Test (VDAT) 2014, IEEE Xplore.

  57. "A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip"
    N. K. Meena, H. K. Kapoor and S. Chakraborty
    18th International Symposium on VLSI Design and Test (VDAT) 2014, IEEE Xplore.

  58. "Cache Capacity and its Effects on Power Consumption for Tiled Chip Multi-Processors"
    S. Chakraborty, D. Deb, D. Buragohain and H. K. Kapoor
    International Conference on Electronics and Communication Systems (ICECS)
    2014, IEEE Xplore.

  59. "A Reduced Overhead Replacement Policy for Chip Multiprocessors having Victim Retention"
    S. Das, D. Buragohain and H. K. Kapoor
    International Conference on Electronics and Communication Systems (ICECS)
    2014, IEEE Xplore.

  60. 2013

  61. "Towards a Better Cache Utilization Using Controlled Cache Partitioning"
    P. D. Halwe, S. Das and H. K. Kapoor
    11th IEEE International Conference on Embedded Computing (EmbeddedCom2013), IEEE
    pp. 179-186, 2013, IEEE.

  62. "Dynamic Associativity Management using Fellow Sets"
    S. Das and H. K. Kapoor
    Proc. of the 4th International Symposium on Electronic System Design (ISED 2013), IEEE
    pp. 133-137, 2013, IEEE

  63. "Random-LRU: A Replacement Policy For Chip Multiprocessors"
    S. Das, P. Nagaraju, P. Halwe and H. K. Kapoor
    Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013),
    Communications in Computer and Information Science, vol. 382, pp. 204-213, Springer

  64. 2012

  65. "Modelling and Verification of Compensating Transactions using the Spin Tool"
    K. Wan, H. K. Kapoor, S. Das, B. Raju, T. Krilavicius and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS)
    pp. 1163-1168, March 2012, Hong Kong. IAENG

  66. 2011

  67. "An Authenticated Encryption based Security Framework for NoC Architectures"
    H. K. Kapoor and K. Sajeesh
    Proc. of the International Symposium on Electronic System Design (ISED),
    pp. 134-139, Dec 2011, IEEE

  68. "Highly Resilient Minimal Path Routing Algorithm for Fault Tolerant Network-on-Chips"
    K. L. Man, K. Yedluri, H. K. Kapoor, C-U Lei, E. G. Lima and J. Ma
    Proc. of the International Conference on Advances in Control Engineering and Information Science (CEIS),
    Volume 15, pp 3406-3410, Procedia Engineering, 2011, Elsevier

  69. "Performance Improvement by N-Chance Clustered Caching in NoC based Chip Multi-Processors"
    R. Yarlagadda, S. R. Kuppannagari and H. K. Kapoor
    Proc. of the International Conference on Computer Design (CDES)

  70. "Clustered Caching for Improving Performance and Energy requirements in NoC based Multiprocessors"
    H. K. Kapoor, L. Chatterjee and R. Yarlagadda
    Proc. of the International Conference on Computer Design (CDES)

  71. "Towards a Language Based Synthesis of NCL Circuits"
    H. K. Kapoor, A. Asthana, T. Krilavicius, W. Zeng, J. Ma and K. L. Man
    Proc. of The International MultiConference of Engineers and Computer Scientists (IMECS),
    pp. 1033-1038, March 2011, Hong Kong. IAENG (Certificate of Merit)

  72. 2010

  73. "Process Algebraic Specification of DI Circuits"
    K. L. Man, A. Asthana, H. K. Kapoor, T. Krilavicius and J. Chang
    Proc. of the 7th IEEE International SoC Design Conference (ISOCC), pp. 396-399, Nov 2010. Korea. IEEE

  74. "Fair diagnosability in PN-based DES models"
    A. Khan, K. Misra, S. Biswas, J. Deka and H. K. Kapoor
    Proc. of the 8th IEEE International Conference on Control and Automation (ICCA), 2166 - 2171, 2010, IEEE.

  75. "Interface Process Generation to Compose Delay-Insensitive Asynchronous Modules"
    H. K. Kapoor
    Proc. of the International Conference on Communication, Computers and Devices (ICCCD), India, 2010

  76. "Exploring use of NoC in Reconfigurable Video Coding"
    A. Patel and H. K. Kapoor
    Proc. of 23rd IEEE International Conference on VLSI Design, pp. 134-139, Jan 2010

  77. 2009

  78. "Mixed clock FIFO Design"
    R. Yarlagadda, J. Karthik and H. K. Kapoor
    Proc. of the 13th VLSI Design And Test Symposium (VDAT), Bangalore, India, 2009

  79. 2007

  80. "Modelling Latency-Insensitive Systems in CSP"
    H. K. Kapoor
    Proc. of the 7th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp 231-232, July 2007

  81. 2006

  82. "Formal Modelling and Verification of an Asynchronous DLX Pipeline"
    H. K. Kapoor
    Proc. of the 4th IEEE International Conference on Software Engineering and Formal Methods (SEFM), pp. 118-127, Sep 2006

  83. 2005

  84. "Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation"
    H. K. Kapoor and M. B. Josephs
    Proc. of the 5th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 58-67, June 2005

  85. 2004

  86. "Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Proc. of the 4th IEEE International Conference on Application of Concurrency to System Design (ACSD), pp. 89-98, June 2004

  87. "Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis"
    H. K. Kapoor and M. B. Josephs
    Proc. of 41st ACM Design Automation Conference (DAC), pp. 830-833, June 2004

  88. 2003

  89. "Computer-aided Synthesis and Verification of Delay-insensitive Protocols"
    H. K. Kapoor, M. B. Josephs and D. P. Furey
    Demonstration at the University Booth of the DATE Conference, Germany, March 2003

  90. "Automated Transformation of Delay-Insensitive Sequential Processes"
    H. K. Kapoor and M. B. Josephs
    Poster in First EDAA Ph.D. Forum at the DATE Conference, Germany, March 2003

  91. 2002

  92. "Handshaking Expansion versus Delay-Insensitive Sequential Processes"
    H.K. Kapoor and M.B. Josephs
    in EPSRC PREP2002, Univeristy of Nottingham, April 2002

Book Chapters

  1. "Formal Modelling and Verification of Compensating Web Transactions"
    S. Das, S. Chakraborty, H. K. Kapoor and K. L. Man
    ITET, World Scientific, 2013.

  2. "Formal Verification and Synthesis of NULL Conventional Logic Circuits"
    H. K. Kapoor, J. Ma, T. Krilavicius, K. L. Man and C-U. Lei
    IAENG Transactions on Engineering Technologies, Volume 7,
    World Scientific, 2012.

Ph.D. Thesis

  • H. K. Kapoor, "Delay Insensitive Processes: A Formal Approach to the Design of Asynchronous Circuits", July 2004. [abstract]