Department of Electronics and Electrical Engineering
Indian Institute of Technology Guwahati
Guwahati-781039, India

EEE Department, IIT Guwahati

Dr. Gaurav Trivedi

pkb
Homepage
Ph.D. (Indian Institute of Technology, Bombay)
Designation: Associate Professor

Dr. Gaurav Trivedi joined the institute in 2011.

Contact Details
Office Address: Room No. #008, G-Block, Academic Complex, IIT Guwahati
Phone: +91-361-2582536 (O)
Fax: +91-361-2582542, 2690762
Email: trivedi[AT*]iitg.ac.in

Research Areas
  • Circuit Simulation (Analog & Digital) and VLSI CAD
  • Electronics System Design
  • Computer Architecture
  • Semiconductor Devices
  • Hardware Security
  • Embedded Systems and IoT
  • High Performance Computing
  • Large Scale Optimization and Machine Learning
Selected Publications
  • Sukanta Dey, Sukumar Nandi, Gaurav Trivedi, “Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-Chip Power Grid Network”, accepted to be published in ACM Transactions on Design Automation of Electronic Systems (TODAES), May, 2020.
  • S. Hussain, R. Kumar, G. Trivedi, "Methodology and Comparative design of an efficient 4-bit Encoder with bubble error corrector for 1-GSPS Flash type ADC", Accepted to be published in IET Circuits, Devices & Systems, doi:  10.1049/iet-cds.2019.0499, April 2020.
  • Sunil Dutt, Satyabrata Dash, Sukumar Nandi and Gaurav Trivedi, “Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders”, IEEE Transactions on Computers, Volume 68, Issue 3, March 2019, pp. 314-330
  • Dheeraj Kumar Sinha, M. S. Ansari, Ashok Ray, Gaurav Trivedi, Amitabh Chatterjee, and Ronald D. Schrimpf, “Fast Ionization-front Induced Anomalous Switching Behavior in Trigger Bipolar Transistors of Marx-bank Circuits Under Base-drive Conditions”, IEEE Transactions on Plasma Science, Volume 46, Issue 6, May 2018, pp. 2064-2071.
  • Sunil Dutt, Sukumar Nandi, Gaurav Trivedi, "Analysis and Design of Adders for Approximate Computing", Transactions on Embedded Computing Systems (TECS), Volume 17 Issue 2, Article 40, December 2017.
  • Gaurav Trivedi, H. Narayanan, “Application of Fast DC Analysis to Partitioning Hypergraphs”, ISCAS 2007, pp. 3407-3410.
  • Gaurav Trivedi, Madhav P. Desai, H. Narayanan, “Parallelization of DC Analysis through Multiport Decomposition”, VLSI Design 2007, pp. 863-868.
  • Gaurav Trivedi, Sumit Punglia, H. Narayanan, “Application of DC Analyzer to Combinatorial Optimization Problems”, VLSI Design 2007, pp. 869-874.
  • Gaurav Trivedi, Madhav P. Desai, H. Narayanan, “Fast DC Analysis and Its Application to Combinatorial Optimization Problems”, VLSI Design 2006, pp. 695-700.
  • G. Anil Kumar, Gaurav Trivedi, Madhav P. Desai, H. Narayanan, “Parallelization of DC Analyzer”, 6th International Conference and Exhibition on High Performance Computing (HPC) in Asia Pacific Region - HPC Asia 2002.