Updated on 26th November, 2024
- The selection process for Ph.D. in the Department of Electronics and Electrical Engineering (EEE) will be held from 27th Nov. 2024 to 29th Nov. 2024
- The list of candidates shortlisted for the upcoming Ph.D. programme admission interviews (December 2024 Session) has been announced. The applicants can check their status in their respective logins on the Application portal. (Link: https://www.iitg.ac.in/admission/login)
- Candidates are requested to visit this webpage regularly for updates.
- Seat Matrix: The seat matrix for Ph.D. admissions in December 2024 session is as follows:
Programme Name | Total | OPEN | GEN-EWS | OBC-NCL | SC | ST |
---|---|---|---|---|---|---|
Ph.D. | 22 | 4 | 4 | 5 | 7 | 2 |
Joint Degree (JD) Ph.D.: JD_EE_RS-SB | 1 | Any |
Table 1: Seat Matrix for Ph.D/JDP
OFFLINE WRITTEN TEST (IATMLA) CANDIDATES:
-
Candidates who have not qualified GATE but have completed their M.Tech Degree and have been shortlisted for written test will have to appear for the offline written test (IATMLA) at IIT Guwahati on 27th Nov. 2024.
-
Candidates appearing for offline written exam (IATMLA) will be interviewed in offline mode by the interview panels only after qualifying the offline written exam (IATMLA). Candidates will not be interviewed if they fail to qualify the written exam.
-
Please note that, candidates will be allowed to appear for written exam for only one specialization based on the first panel preference, as mentioned in the online panel preference form. However, if you qualify the exam of your first panel preference you can appear for offline interview in one additional panel, if you wish to do so, as indicated by you in the online panel preference form.
-
Reporting Time for the Written Test (IATMLA): All candidates shortlisted for the written test need to report to Room no. 2202 (Second Floor of Core 2, EEE Department, Academic Block, IIT Guwahati) for document verification (documents mentioned in the interview call letter) by 8:45 AM on 27th Nov. 2024. Your written test will commence from 10.00 AM on 27th Nov. 2024.
INFORMATION REGARDING THE INTERVIEW PROCESS::
-
Reporting Time for Interview: The interviews will be held offline for all candidates (including those who have qualified IATMLA). So, the shortlisted candidates have to appear physically for the selection process.
-
The interviews will commence from 9:00 AM on 28th Nov. 2024. In case, interview process is not completed on 28th Nov. 2024, then only the interview will be continued on 29th Nov. 2024.
-
Candidates shortlisted for the interview need to report to EEE Department at 8:45 AM, 28th Nov. 2024 for document verification without fail
-
The interviews will be conducted through SIX specialization panels (as mentioned in Table 2 below). The candidates are required to fill up their panel preferences form (sent in email with call letter) before Nov. 25, 2024, in which you will enter at most TWO panel preferences, for which you wish to be interviewed.
-
Please note that the panel preferences for all candidates should be based on the panels mentioned in your application form only.
-
Candidates who have applied for more than 2 panels may check which panel align to their research interests from the link given here.
-
For candidates who do not fill the online panel preference form, sent via email together with interview call letter, before the deadline, the choices mentioned in the application form will be considered to be their final preference.
JDP CANDIDATES
-
The interviews for Joint Degree Ph.D. (JDP) programmes will be conducted in the specialization panels as indicated in Table 2 below. . If a candidate is shortlisted in any of these programmes and wishes to appear for the respective interview(s), they must choose the corresponding panel(s) among theTWO preferences. Please note that under no circumstance will you be allowed to appear for more than TWO interviews.
Specialization Panel Panel Code Communication Engineering CE Signal Processing and Machine Learning SPML Microelectronics, Photonics and RF Engineering / JDP programme: JD_EE_RS-SB MPRF VLSI and Nano-Electronics VLSI Systems, Control and Automation SCA Power Engineering PE Table 2: Details about the six specialization panels/ research groups and their associated faculty members can be seen from the link given here.
SHORTLISTING CRITERIA:
Programme | Shortlisting Criteria |
---|---|
Ph.D. Programmes |
|
TRAVEL REIMBURSEMENT, ACCOMMODATION AND MEAL:
Topic | Important Information |
---|---|
Travel Reimbursement |
|
Paid Accommodation/lodging |
|
Meal | You may avail food at the available hostel messes on a pay-and-eat basis. |