/* * Actual data storing, data movement and LRU policy not implemented * For LRU: for every index we can have a 6 bit counter and every set have a LRU register, when there is a access to a set of an index the counter value of the index is incremented and copied to the LRU register of the set. At the time of replacement, cache block with smallest LRU value of the index get replaced. * */ #include #include #include #include #define HIT 1 #define MISS 0 using namespace std; class Cache { private: int set, asso, LS; int hit_counter,miss_counter; int **TAG; public: int get_hit(void){return hit_counter;} int get_miss(void){return miss_counter;} Cache(){} void CacheInit( int sets, int associativity, int LineSize ) { int i, j; TAG = new int*[sets]; for(i = 0; i < sets; i++) TAG[i] = new int [associativity]; assert( TAG != NULL ); /* Initialize tag to be -1 */ for(i=0;i