Course Structure:

• Boolean Algebra and switching functions; Minimization and realization using logic gates, ROMs, PLAs, multiplexers; Circuits for code conversion;
• Flip-flops, registers, counters; Finite state model: State tables and diagrams; State minimization; Excitation functions of memory elements; Synthesis of synchronous sequential circuits; Representation and synthesis using ASM charts; Incompletely specified machines; Specification and synthesis of asynchronous sequential machines; Number representation: fixed and floating point; Addition, subtraction, multiplication and division of numbers. Current trends in digital design: ASIC, FPGA, etc.;

Lectures: Post Mid Sem part

1. 25 SEP 2019 (THU): Sequential Circuit, Latch, RS Latch, Race Condition, Ensure no RS=11, Stabilize with Enbale/C, Store (Level Sensitive Latch) [[ Ref Section 3.1 of VahidBook, Ref Section 5.2 and 5.3 of ManoBook]] PDF Slides

Text Books:

1. ManoBook: M. Morris Mano and M. D. Ciletti, Digital Design, 4/e, Pearson Education India, 2007.
2. KumarBook: A. Anand Kumar, Fundamentals of Digital Circuits 3rd Edition, PHI. 2014 ((This book have a lot of examples to understand the concepts))

1. GivoneBook: Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003
2. VahidBook: Frank Vahid, Digital Design (Preview Edition), Wiely India Edition, 2005
3. KatzBook: Randy H. Katz, G Borriello, Contemporary Logic Design, 2nd Edition, PHI, India, 2009
4. HDLBook: Douglas L. Perry, VHDL: Programming By Example , 4th Edition, Mcgraw Hill Education, 2008 PDF Version
5. VHDL Primer by J Bhaskar A good book to written consizely

Class timing, Venue and Rules:

• Venue: L1, Timing: Wed 9AM-10AM, Thu 10AM-11APM, and Fri 11AM-12Nn
• Post mid sem part will have 3 quizes, each carrying 5% of total mark
• End sem carry 35% of post-mid sem part