CS221 Digital Design (Instructors: Dr Santosh Biswas and Dr. A. Sahu)
Course Structure | Lecture Slides | Books | ClassTiming, Venue and Rules
- Boolean Algebra and switching functions; Minimization and realization using logic gates, ROMs, PLAs, multiplexers; Circuits for code conversion;
- Flip-flops, registers, counters; Finite state model: State tables and diagrams; State minimization; Excitation functions of memory elements; Synthesis of synchronous sequential circuits; Representation and synthesis using ASM charts; Incompletely specified machines; Specification and synthesis of asynchronous sequential machines; Number representation: fixed and floating point; Addition, subtraction, multiplication and division of numbers. Current trends in digital design: ASIC, FPGA, etc.;
Class timing: WED (9-10), THU (10-11) and FRI (11-12Nn)
Monday (5PM-6PM) is reserved for makeup classes and Quiz exam
Lecture slides will be uploaded (to this website) after Quizs.
- 24 SEP 2015 (THU): Sequential Circuit, Latch, RS Latch, Race Condition, Ensure no RS=11, Stabilize with Enable/C, Store (Level Sensitive Latch) [[ Ref Section 3.1 of VahidBook, Ref Section 5.2 and 5.3 of ManoBook]] PDF Slides
- 28 SEP 2015 (MON): Latches Vs FF, Edge Triggered Storage (Master Slave FF), Optimized MS FF with NAND Gate, JK-FlipFlop, T-FF (Make up class of 27 OCT) [[ Sec 5.4, 5.5 of ManoBook]] PDF Slides
- 29 SEP 2015 (TUE): Characteristic Table of FF, Characteristic equation of FF, Register, Register Design PIPO, SISO with Mux input control [[ Ref Section 4.2 of VahidBook, Ref Section 5.4, 5.5, 6.1 and 6.2 of ManoBook]] PDF Slides
- 30 SEP 2015 (WED): Use of SISO, Universal Register, Memory design using register [[Ref Section 4.2 of VahidBook, Ref Section 5.4, 5.5, 6.1 and 6.2 of ManoBook ]] PDF Slides
- 01 OCT 2015 (THU): Counter Design: Ripple counter, Mod counter, Up-Down counter, Synchronous counter, Counter based on Shift Register [[Ref Section 6.3, 6.4 and 6.5 of Mano Book ]] PDF Slides
05 OCT 2015 (MON): Quiz (Monday 5PM-6PM Lecture Hall 2 (LH2)) Quiz With Partial Sol
- 07 OCT 2015 (WED): Finite State Machine (FSM), Formalizing Sequence, States, Transition, State Transition Diagram, State Transition Table, Modeling D FF using FSM, Modeling T, JK FF using FSM, Modeling 2 bit PIPO Register using FSM, Modeling 2 bit RightShift-SIPO using FSM [[Ref Sectio 5.5, 6.1 and 6.2 of ManoBook, Ref Section 3.3 of VahidBook, Ref Sec 7.2 of KatzBook ]] PDF Slides
- 08 OCT 2015 (THU): FSM : Example (Parity Encoder, Sequence Detector, Traffic Signal, Laser Signal, Security Lock) [[Ref Section 3.3 and 3.4 of VahidBook ]] Continuation of Prev Lecture
- 09 OCT 2015 (FRI): FSM Controller : Design Procedure (Spec, Model, Reduce, Tabularize, CC, Decoding State to Output) [[Ref Section 3.3 and 3.4 of VahidBook ]] PDF Slides
- 10 OCT 2015 (SAT): Designing Counter using FSM, Unused state and self-starting counter, Benefit of using JK FF instead of D-FF, T- FF and SR-FF [[Sec 6.9 GivoneBook]] PDF Slides
- 14 OCT 2015 (WED): Mealy FSM Vs Moore FSM, Examples, Advanced FSM Design and Optimization, State Minimization: Row Matching Method, Implication Cart Method, FSm Partitioning [[Ref Sec 7.3.2, 8.1, 8.2 of KatzBook, Sec 9.5 of ManoBook, Sec 7.4 and 9.2 of GivoneBook]] PDF Slides
- 15 OCT 2015 (THU): State Encoding: Sequential, Random, One Hot, Output Oriented, Heuristics based encoding [[Ref Sec 8.1, 8.2 of KatzBook ]] PDF Slides
26 OCT 2015 (MON): Quiz (Monday 5PM-6PM Lecture Hall) Quiz With Partial Sol
- 28 OCT 2015 (WED): VHDL: Requirement of any HDL languages, IC Design flow, Processor and Application Specific IC chip, embedded system product (calculator, remote, projector,..,etc) [[ ]] PDF Slides
- 29 OCT 2015 (THU): VHDL hello world program, HDL introduction, CLB, FPGA Architecture [[Ref: Sec 7.8 of ManoBook ]] PDF Slides
- 30 OCT 2015 (FRI) : FPGA and CLB, Sythesizable HDL, Synthesis Tools or EDA Tools, CLB internal, Configurable 3x1 function block using 1bitX8address memory, [[... ]]
- 04 NOV 2015 (WED) : HDL Syntax and Construct [[HDLBook ]] PDF Slides
- End Sem Solution End Sem Solution PDF
VHDL Resources
- 05 NOV 2015 (THU) : VHDL Examples: Process, Process sensitivity list, wait [[HDLBook ]] PDF Slides
- 06 NOV 2015 (FRI) : Generic, Generate construct of HDL, VHDL Examples: Mux, FSM in HDL, Register, FA, nbit RCA, Structural and Behavioural FA [[HDLBook, GHDL Demo of hello world, Adder and adder test bench in Window version of GHDL]] PDF Slides
09 NOV 2015 (MON): Quiz (Monday 5PM-6PM Lecture Hall) Quiz With Partial Sol
- 12 NOV 2015 (THU): Number representation (Int, Float) [[ PDF Slides ]]
- 13 NOV 2015 (FRI): Operations (ADD, MUL), RTL Design for Multiplier [[ PDF Slides ]]
- 16 NOV 2015 (FRI): Operations (ADD, MUL), RTL Design for Multiplier [[ ]]
- ManoBook: M. Morris Mano and M. D. Ciletti, Digital Design, 4/e, Pearson Education India, 2007.
- KumarBook: A. Anand Kumar, Fundamentals of Digital Circuits 3rd Edition, PHI. 2014 ((This book have a lot of examples to understand the concepts))
References Books:
- Givone Book: Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003
- VahidBook: Frank Vahid, Digital Design (Preview Edition), Wiely India Edition, 2005
- KatzBook: Randy H. Katz, G Borriello, Contemporary Logic Design, 2nd Edition, PHI, India, 2009
- HDLBook: Douglas L. Perry, VHDL: Programming By Example , 4th Edition, Mcgraw Hill Education, 2008 PDF Version
- VHDL Primer by J Bhaskar A good book to written concisely
- Venue: 1207, Timing: Tues 4PM-5PM, Wed 3PM-4PM, and Thurs 2PM-3PM
- Weightage : Scribe 15%, Mid Sem 30%, 3 Quizs 21%, End Sem 34%
- Scribe will be for pre-mid sem part, please contact Santosh Biswas for this
- Post mid sem part will have 3 quizes, each carrying 7% of Total Mark
- End sem carry 34% out of which 5% will be from pre mid sem part and 29% will be from post mid-sem part