CS 522, Embedded Systems
Spring 2008 - 2009
Purandar Bhaduri, ext: 2360 (Email: pbhaduri)
C. Surendranath Chowdary (email: c.chowary)
Suman Das (email: sumandas)
Gaurav Makhon Baruah (email: g.baruah)
CS203 (Discrete Maths)
CS 221 (Digital Design)
CS 222 (Computer Organization and Architecture).
The author’s course material (including lecture slides).
You may refer to the following books for additional reading.
1. W. Wolf, Computers as components: principles of embedded computing system design. Morgan Kaufmann, 2005.
2. G.C. Buttazzo, Hard real-time computing systems: predictable scheduling algorithms and applications. Kluwer Academic Publishers, 2005.
3. H. Kopetz, Real-time system design principles for distributed embedded applications, Springer, Indian edition, 1997.
Assignments, Seminar/Term Paper 20%
1. ARTIST Network of Excellence on Embedded Systems Design is an excellent source containing a wealth of material on research on embedded systems. In particular, look at the Dissemination and Course Material Available Online page.
4. The synchronous hypothesis and synchronous languages, D. Potop-Butucaru, R. De Simone, J.-P. Talpin, in The Embedded Systems Handbook, CRC Press, 2005. See also, The Synchronous Languages Twelve Years Later, A. Benveniste et al, Proc. of the IEEE, 91(1), special issue on Embedded Systems, 64-83, Jan 2003.
6. The original Statecharts model proposed by David Harel
a. Statecharts: A Visual Formulation for Complex Systems, David Harel, Science of Computer Programming 8(3): 231-274 (1987). Copy from the author’s website.
b. STATEMATE: A Working Environment for the Development of Complex Reactive Systems, David Harel, Hagi Lachover, Amnon Naamad, Amir Pnueli, Michal Politi, Rivi Sherman, Aharon Shtull-Trauring, Mark Trakhtenbrot, IEEE Trans. Software Eng. 16(4): 403-414 (1990)
a. The UML Resource Page from OMG.
b. UML 2.0 Tutorial by Ileana Ober.
c. Unified Modeling Language 2.0 by Harald Störrle and Alexander Knapp.
Object Modeling with Statecharts", D. Harel and
f. "Class 505/525: State machines and Statecharts", Bruce Powel Douglass, Proceedings of Embedded Systems Conference, San Francisco 2001.
g. Rhapsody: A Complete Life-Cycle Model-Based Development System, Eran Gery, David Harel, Eldad Palachi, IFM 2002, pp 1-10.
8. Free copy of Real-Time Systems: Specification, Verification and Analysis, Mathai Joseph, Ed. Prentice-Hall, 1995.
Some Important Papers
1. Embedded System Design for Automotive Applications, A. Sangiovanni Vincentelli, M. Di Natale, IEEE Computer, Vol 40 (10), Oct. 2007, pp 42-51.
2. Design of Embedded Systems: Formal Methods, Validation and Synthesis, S. Edwards, L. Lavagno, E. Lee, A. Sangiovanni-Vincentelli, Proceedings of the IEEE, vol. 85 (n.3) - March 1997, pp 366-290.
3. System level design paradigms: Platform-based design and communication synthesis, A. Pinto et al, ACM Transactions on Design Automation of Electronic Systems 11(3): 537-563 (2006). See also, Platform-Based Design for Embedded Systems, L. Carloni et al, in R. Zurawski (Ed.), The Embedded Systems Handbook, CRC Press , 2005 and System design: traditional concepts and new paradigms, A. Ferrari and A. Sangiovanni-Vincentelli, International Conference on Computer Design 1999 (ICCD '99), pp 2-12.
4. The Discipline of Embedded Systems Design, T. A. Henzinger and J. Sifakis, IEEE Computer Vol. 40, Issue 10, pp 32-40, 2007.
5. The embedded systems design challenge, Thomas A. Henzinger and Joseph Sifakis, Proceedings of the 14th International Symposium on Formal Methods (FM), Lecture Notes in Computer Science 4085, Springer, 2006, pp. 1-15.
6. From Control Loops to Real-Time Programs, P. Caspi and O. Maler, Handbook of Networked and Embedded Control Systems, 395-418, 2005.
7. Real Time Scheduling Theory: A Historical Perspective, L. Sha et al, Real-Time Systems 28(2-3): 101-155 (2004).
8. Scheduling algorithms for multiprogramming in a hard-real-time environment, C.L. Liu and J.W. Layland, J. ACM Vol. 20 (1), 1973, pp. 46–61.
9. Liu and Layland's schedulability test revisited, Raymond R. Devillers and Joël Goossens, Inf. Process. Lett. 73(5-6): 157-161 (2000).
A Time-triggered Language for Embedded Programming, T. A. Henzinger, B.
Horowitz, and C. M. Kirsch, Proceedings of the IEEE 91:84-99, 2003. See also
the Giotto page at
11. The time-triggered architecture, H. Kopetz and G. Bauer, Proceedings of the IEEE, 91(1):112--126, January 2003.
12. Timed Automata, R. Alur, NATO-ASI 1998 Summer School on Verification of Digital and Hybrid Systems. See also, Timed Automata: Semantics, Algorithms and Tools, J. Bengtsson and W. Yi, Lectures on Concurrency and Petri Nets 2003, pp 87-124 and Foundation for Timed Systems, P. Bouyer, ARTIST2 Summer School on Component & Modelling, Testing & Verification, and Static Analysis of Embedded Systems, Sept 29 - Oct 2, 2005.
1. The license keys for Esterel Studio and SCADE are installed on the Linux server loktak. You need to download and install the software from the CSEA site. The instructions on how to install the license keys are here. For more help, consult the installation guidelines. Public domain Esterel tools are available from INRIA.
No late submissions will be accepted! The work must be done on your own. Two or more identical or near identical solutions will get zero credit.
1. Use Esterel Studio to model and simulate the VME bus controller described in sections 5 and 6 of the paper “Analysis of VME-Bus communication protocol - RTCP-net approach”, Marcin Szpyrka, Real-Time Systems 35(1): 91-108 (2007). Show your results to the TA assigned to you. The due date is Monday, 16 March 2008.