-------------------------------------------------------- Project Students -------------------------------------------------------- PhD: July 2021-till date 11. Rishabh Mahanta Doing course work Jan 2021-till date 12. Neeraj Sharma (joint student) Networks July 2020-till date 11. Swati Upadhyay Multi-processor Computer Architecture July 2019-till date 10. Imlijungla Longchar ML accelerators July 2018-till date 9. Aswathy N. S. Memory Controllers July 2016-till date 8. Arijit Nath Multi-processor Computer Architecture Jan 2016-till date 7. Sheel Sindhu Manohar Multi-processor Computer Architecture July 2015-April 2022 (defended) 6. Palash Das Near-Memory acceleration of Convolutional Neural Networks by exploiting Parallelism, Sparsity, and Redundancy [Awarded Intel fellowship] [Examiners: Prof. Adwait Jog (College of William and Mary, USA), Prof. Preeti Ranjan Panda (IIT Delhi) July 2017 - July 2020 (submitted) - Jan 2021 (defended) 5. Khushboo Rani LongLiveNoC: Wear Levelling, Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects [Examiners: Prof. Mark Zwolinski (University of Southampton, UK), Prof. Santanu Chattopadhyay (IIT Kharagpur)] July 2014 - Sep 2019 (submitted) - Mar 2020 (defended) 4. Sukarn Agarwal LiNoVo: Longevity Enhancement of Non-Volatile Caches by Placement, Write-Restriction & Victim Caching in CMPs [Awarded TCS fellowship] [Examiners: Prof. Jaydeep Kulkarni (The University of Texas at Austin), Prof. Kolin Paul (IIT Delhi)] Jan 2014 - July 2019 (submitted) - Mar 2020 (defended) 3. Sanjay Moulik [Jointly with Dr. Arnab Sarkar] New Approaches to Energy and Temperature Aware Scheduling Techniques for Real-time Multi-core Systems [Examiners: Prof. Partha S. Roop (University of Auckland) Prof. Ansuman Banerjee (ISI Kolkata)] Jan 2012 - October 2017 (submitted) - Feb 2018 (defended) 2. Shounak Chakraborty ++ Assistant Professor at IIIT Guwahati, Post-Doc fellow at NTNU Norway Energy and Thermal Management of CMPs by Dynamic Cache Reconfiguration [Examiners: Prof. Pierfrancesco Foglia (Pisa), Prof. Bhargab B. Bhattacharya (ISI Calcutta)] Jan 2011-August 2015(submitted)-Jan 2016(defended) 1. Shirshendu Das ++ Assistant Professor at IIIT Guwahati, now at IIT Ropar Effective Utilization of LLCs by Managing Associativity, Placement and Mapping [Awarded TCS fellowship] [Examiners: Prof. Rajeev Balasubramonian (Utah), Prof. Madhu Mutyam (IITM)] -------------------------------------------------------- 2022-23 MTech: 42. Zeeshan Anwar Accelerator Design for Machine Learning 41. Aishwarya Gupta Memory request scheduling 40. Venkatesh Yekbote Non-Volatile memories BTech: 47. Dyuti Mangal Accelerator Design for Machine Learning 46. S. Roshan Accelerator Design for Machine Learning 45. Akshat Sinha Non-Volatile memories 2021-22 MTech: 39. Nishant Bharti Bit level compression by removing longest sequence of zeros/ones to enhance lifetime of Non-Volatile Memories 38. Chetan Pralhad Ingle Reducing Computations in Deep Convolutional Neural Networks by exploiting approximation and Static Sparsity 37. Deep Bhuinya Enhancing lifetime of Phase Change Memory by write variation-aware address remapping BTech: 44. Saurabh Baranwal Accelerator Design for Machine Learning 43. Amey Varhade Accelerator Design for Machine Learning 2020-21 MTech: 36. Yash Soni Optimising the number of computations in Compressed Sensing 35. Shashank Maurya Fast Tensor Decomposition by DP implementation of Khatri Rao Product in MTTKRP 34. Mayank Sharma Network on Chip BTech: 42. Shashank Sharma CNN Inference Acceleration using Look-up Tables 41. Siddarth Agarwal An FPGA-based Accelerator for Convolutional Neural Networks 40. Autonu Kro Network on Chip 2019-20 MTech: 33. Manik Bhosle Securing Non-Volatile Memory by Selective Page Placement in Hybrid Main Memory 32. Satyam Ankur ANN-based Power Gating for Networks on Chip BTech: 39: Pradeepa Seelam Analysis of Fault Tolerant Methods in Different Sectors of NoC 38: Lakshmi Sai Durga Myneni Analysis of Fault Tolerant Methods in Different Sectors of NoC 37: Harshit Srivastava Power gating of NoC Links using Reinforcement Learning 36: Divyansh Sharma Power gating of NoC Links using Reinforcement Learning 2018-19 MTech: 31. Rodney Stephen Rodrigues SelSpec: SELectively Shielding SPECulative Loads to Guard Against Spectre Attack 30. Neelkamal i-MAX : Just-in-Time Wakeup of Maximally Gated Router for Energy Efficient Multi NoC BTech: 35: Shanigaram Bharath Chandra Traffic based DVFS for Networks on Chip 34: Sowdaboina Sai Harsha Vardhan Traffic based DVFS for Networks on Chip 33: Lakshmireddy Sesha Sai Shobith Hardware Modules for Image Processing 2017-18 MTech: 29. Thiyam Susma Devi Fault Tolerance Routing Algorithm in Network on Chip BTech: 32: Dasari Bindu Bharadwaj Hardware Modules for Image Processing 2016-17 MTech: 28. Lt. Col. Alankar V. Umdekar Controlling Chip Temperature by using Task Migration in Conjunction with Frequency Scaling 27. Sourabh H. Gavhale Latency-aware Routing Over Bypass Channels for Power-Gated On-Chip Networks 26. Priya Sharma Fault Tolerant ByPass Path based Routing Algorithm for Network on Chip BTech: 31. Shivam Lakhotia ++ Masters from UCSD Near Data Processing for Convolutional Neural Networks 30. Prabodh Shetty ++ Masters from UMass Near Data Processing for Convolutional Neural Networks 29. Abhinav Sonkar Fault-Tolerant Routing Mechanism in Networks-on-Chip for Multiple Faults 28. Shashank Suman Fault-Tolerant Routing Mechanism in Networks-on-Chip for Multiple Faults 2015-16 MTech: 25. Gibran Iqbal Analysing the Effects of Task Migration and Frequency Scaling on Temperature of Chip Multiprocessors 24. Gopayya Fault tolerant routing in NoC 23. Dipika Deb A Cost Effective Adaptive Routing Model for 2D Mesh NoC using on-chip Transmission Lines BTech: 27. Himanshu Goyal Computer Architecture 26. Radhika Patodiya Computer Architecture 25. Pokkula Sathwik Sai NoC Interconnects 24. Devarakonda Uday Kumar NoC routing 2014-15 MTech: 22. Sanket Kishor Dayma Static Energy Reduction by Selective Bank Shutdown 21. Devendra Malviya Implementation of Bus Interconnect for Chip Multiprocessors 20. Vivek Kumar Chaurasia Utility Based Cache Partitioning with Insertion and Promotion Policies BTech: 23. Bhavya Madan Cache Partitioning methods 22. K. Yoshitha Real Time Scheduling 21. Jaswinder Singh Network on Chip Routing Algorithms 2013-14 MTech: 19. Kartheek Vanapalli Searching Mechanisms for Dynamic NUCA in Chip Multiprocessors 18. R. Dinesh Replacement Methods for Dynamic NUCA in Chip Multiprocessors BTech: 20. Arpit Agarwal Hybrid Cache Management Policies for Shared L2 Cache in Chip Multiprocessors 19. Anuradha Raju Minimally Buffered Routers in Networks-on-Chip 18. Vivek Rajwar Fault Tolerant Routing Algorithms for Networks-on-Chip 2012-13 MTech: 17. Prateek Halwe Controlled Cache Partitioning of Multicore LLC 16. Manojit Ghosh Hybrid Cache Replacement Policy to Reduce Number of Misses in LLC BTech: 17. Apoorv Kumar Wireless NoC (WiNoC) Architectures 16. Narendra Kumar Meena Multicast Routing in 3D Networks On Chip 15. Vibhuti Kumar Web Service for Car Broker System 2011-12 MTech: 15. P. Nagaraju Reserve Caching for Improving Performance in Chip Multi-Processors 14. M. Lakshmi Prasad Novel Approach for Multi-cast Routing in Network-on-Chip 13. B. Venkateshwarlu Naik Real Time Dynamic Voltage and Frequency Scaling(RT-DVFS) for Power Optimization in Multi-processor Real Time Systems 12. Raju Bairishetti Modelling and Verification of Compensating Transactions BTech: 14. Sharique Arshi Wormhole Router Architecture for NoC: Design and Optimisation 13. Keloth Kumar Fault Tolerant Routing Algorithm for NoC without using Virtual Channels 12. Raj Vardhan Ampili Reconfigurable Routing Algorithm for Fault Tolerant 2D Mesh NoC 2010-11 MTech: 11. Karthik Yedluri Fault Tolerance in NoC. 10. Malti Verma (co-guide) Formal Verification of Cache Coherence Protocols. BTech: 11. Rakesh Yarlagadda Cache coherence in NoC based systems. 10. K. Sanmukh Rao : ++ PhD Student at Univ. of Southern California Cache coherence in NoC based systems. 2009-10 MTech: 9. Shirshendu Das : ++ PhD Student at Department of CSE, IIT Guwahati Formal Modelling of Latency-Insensitive Systems. 8. Lopamudra Chatterjee Cache coherence in NoC based systems. 7. Lalit Chandnani Formal modelling of dynamic power management. 6. Kushagra Misra (co-guide) Testing of Asynchronous circuits BTech: 9. Abhishek Anand : ++ PhD Student at Department of CSE, Cornell University Machine learning for garbage collection in flash filesystems. 8. Rohith Reddy NoC router micro-architecture. 7. Varun Vihari NoC router micro-architecture. 6. Praveen Kanakala : ++ PG Student at IIM Calcutta Cache coherence in NoC based systems. 5. Suhas Aggarwal Reducer: A tool to reduce redundant disk I/O. 2008-09 MTech: 5. Alpesh Patel NoC for DSP architectures. 4. Sajeesh Security issues in NoC. 3. V. Balakrishna QoS in NoC. BTech: 4. D. Parasara Sridhar : ++ PhD Student at Department of CSE, Univ. of Illinois at Urbana Champaign Formal Modelling of Latency-Insensitive Systems. 2007-08 MTech: 2. Kiran Sawant Formal Verification of Security Protocols. BTech: 3. Alok Kumbhare : ++ PhD Student at School of Engineering, Univ. of Southern California Design and Verification of Mobile Ad-hoc network protocols. 2. Arpit Garg Bio-computing. 1. V. B. Vikram Kumar Bio-computing. 2005-06 MTech: 1. Abhinav Asthana Design and Synthesis of Asynchronous Circuits.