Pre-requisites : CS221 or Equivalent
Introduction: Problem specifications for IC design, IC design flow, High level design, HDL design Synthesis - Full-custom, standard-cell, gate-array and FGPA Timing analysis, Backend, Verification and Test IC description at RTL in HDL(Verilog) Review of key algorithmic concepts in CAD: Paths and circuits, Cut sets and cut vertices, connectivity and separability, isomorphism, binary trees, spanning trees, fundamental circuits, coloring graphs Basic concepts of high-level synthesis: Partitioning, scheduling, allocation and binding Introduction to Combinational Logic Optimization: Review canonical form, PLA format, Elements of Espresso Sequential Circuit Design: approaches to state assignment Physical design automation algorithms: Floor-planning, Partitioning & Placement, partitioning-based techniques (K-L, F-M), Quality metrics & constraints, Routing, Constraint representation, 1-D approaches, 2-D compaction, Global routing, Detailed routing layers, vias, etc. , Generalized routing (Maze), Channel routing.
1. G. De Micheli. Synthesis and optimization of digital circuits, 1st edition, 1994.
2. N. A. Sherwani, Algorithms for VLSI Physical Design Automation, Bsp Books Pvt. Ltd., 3rd edition, 2005.
1. N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, Addison Wesley , 2nd edition, 1994.
2. D. West, Introduction to Graph Theory. Prentice Hall, 2nd edition, 2000.
3. S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall, 2nd edition, 2003.
4. D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992.