Pre-requisites : CS221 or Equivalent
VLSI Design: Combinational logic Synchronous sequential logic Asynchronous sequential logic Topics in SoC Interconnect Topics in Network on Chip. VLSI Testing: Introduction Fault models: Stuck-at faults, Advanced Fault Models Fault Simulation: Serial, Parallel, Deductive, Concurrent Test generation for combinational circuits D algorithm Test generation algorithms for sequential circuits Scan and partial scan design Built in self-test (BIST) Memory testing. Verification Techniques: Introduction to Hardware Verification and methodologies Binary Decision Diagrams(BDDs) and algorithms over BDDs Combinational equivalence checking Temporal Logics modeling sequential systems and model checking Symbolic model checking.
1. J. Nurmi, H. Tenhunen, J. Isoaho and A. Jantsch, Interconnect-centric design for advanced SoC and NoC, Springer, 2004.
2. C. J. Myers, Asynchronous circuit design, John Wiley & Sons, July 2001.
3. M. Mano, Digital Design, 3rd edition, 2001.
4. M. Huth and M. Ryan, Logic in Computer Science modeling and reasoning about systems, Cambridge University Press, 2nd Edition, 2004.
5. Bushnell and Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal Circuits, Kluwer Academic Publishers, 2000.
6. P. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall, 1984.
7. N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 2nd edition, 1994.
8. G. De Micheli and L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann, 2006.
9. R. H. Katz and G. Borriello, Contemporary Logic Design, 2nd edition, Prentice hall, 2005.