High-level Synthesis (HLS) is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. Other phases of EDA like logic synthesis and physical synthesis are matured. There is some progress in HLS technology as well. The researchers have proposed various strategies for scheduling, allocation and binding and data path and controller design, explored the impact of compiler optimizations of HLS synthesis results. However, there are many areas like HLS for FPGA targets, HLS for secure and reliable hardware and particularly the verification of HLS not explored yet properly. As HLS has matured the quality of results has improved dramatically for a much wider range of C coding styles. However, this does not mean that all styles are equal, and there is still thepotential for ending up with poor quality RTL when the C is not well written. Good style not only requires an understanding of the underlying hardware architecture of an algorithm, so that itis reflected in the C design, but also an understanding of how HLS works. The objective of this course is to a comprehensive overview of synthesis, optimization and verification technologies of existing C-based VSLI design. Moreover, the current research trends in C-based VLSI will be discussed. In the last phase, the future research directions in this area will be discussed. This course will help the participant to understand

• The overall C-based VLSI flow,
• How a C-code will be converted to its equivalent hardware,
• How to write c-code for efficient hardware generation,
• How the common software compiler optimization can help to improve the circuit performance,
• HLS for security, HLS for Reliability,
• HLS for FPGA targets,
• Optimizations at RTL level and
• Verification challenges of HLS.

• Dr. Chandan Karfa, Assistant Professor, IIT Guwahati.
• Dr. Ansuman Banerjee, Associate Professor, ISI Kolkata.
• Dr. Arnab Sarkar, Associate Professor, IIT Guwahati.
• Prof. Jatindra Kr. Deka, Professor, IIT Guwahati.
• Dr. John Jose, Assistant Professor, IIT Guwahati.

• Day 1: Introduction to Electronic Design Automation, Introduction to C-Based VLSI Design (High-level Synthesis (HLS)), Scheduling Techniques
• Day 2: Resource allocation and binding, Compiler optimization in HLS, HLS for FPGAs, Lab session on HLS
• Day 3: HLS for security, Fault-tolerant HLS, C coding style for HLS, Lab session on HLS
• Day 4: HLS Verification, Recent Trends in HLS, Lab session on HLS Verification
• Day 5: RTL optimization Techniques, Effective Teaching Pedagogies

The course is open to faculty members of TEQIP mapped institutions. Please refer to "Institution List" link in the NPIU website for list of TEQIP mapped institutions. However, PhD scholars/PG students from these institutions may be accommodated subject to the vacancy of seats. There will be a refundable registration fee of 2500 INR for the participants from TEQIP mapped institutions. Seats that remain unfilled will be open to faculty/students of other institutions with a non-refundable registration fee of 2500 INR. There will be a total of 40 seats for the course based on application followed by shortlisting. The registration fee will cover course materials and working lunch.

1. Take a Demand Draft of 2500 INR drawn in favour of Registrar, IIT Guwahati, payable at Guwahati towards registration fee.
2. Download the course Application Form and fill-up (typesetting is preferred over handwritten) all the entries including DD details.
3. Generate a pdf document of the filled up application form and take a printout of the same.
4. Affix your recent passport size color photograph and put your signature in the respective cells.
5. Download the course Endorsement Form and get it duly approved and signed by the head of your institution. Seal of the institute is mandatory.
6. Send the documents and DD via speedpost to the course cordinator (postal address given below) so as to reach IIT Guwahati latest by 8.3.2019, Friday.
7. Send a soft copy (preferrably pdf) of the duly filled application form to debabratasenapati@gmail.com.
8. Fill this Intimation Form after you have send the application form and the DD via post.

List of selected candidates from TEQIP mapped institutions will be displayed on this website by 12.3.2019. No separate emails will be sent regarding this.
List of selected candidates from non-TEQIP institutions will be displayed on this website by 14.3.2019. No separate emails will be sent regarding this.
Registration Fee DD will be returned back (via speed post), if the candidate is not shortlisted.

For participants from TEQIP mapped institutions, based on request, accommodation can be arranged free of cost in the Institute Guest House for faculty members and student hostels inside IITG campus for research scholars/PG students. Participants from non-TEQIP institutes should make their own arrangements for boarding and lodging. However, we shall assist them to get accommodation inside campus if requested.