Chandan Karfa

CS 577: C-Based VLSI Design: Synthesis, Optimization and Verification

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Cource Overview

• High-level Synthesis (HLS) is the process of generating effecient hardware from C-code (high-level code). HLS is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. This course will help the student to (i) understand the overall HLS flow, (ii) how a C-code will be converted to its equivalent hardware, (iii) how to write c-code for efficient hardware generation and (iv) how the common software compiler optimization can help to improve the circuit performance. Also, advanced topics like Relative Scheduling, IO scheduling modes, handshaking and HLS for FPGA targets, optimizations at RTL level and verification challenges of HLS will be covered. This course will help the students to take up research in the domain of HLS. Also, this course will help the student to become proficient for EDA industries.

• Pre-requisites: (1) Basic knowledge of digital circuits (2) Basic knowledge of Data structures and algorithms

Instructors

• Dr. Chandan Karfa

Class Timing and Venue:

• Friday: 9AM-9:55AM, Monday: 10AM-10:55AM, Tuesday: 11AM-11:55AM

• Venue: 3102

Syllabus:

• Electronic Design Automation flow: Overview of high-level synthesis, logic synthesis and physical synthesis;

• High-level Synthesis (HLS) Fundamentals: Overview HLS flow, Scheduling Techniques, Resource sharing and Binding Techniques, Data-path and Controller Generation Techniques;

• Impact of C-coding style on Hardware: Data types, Synthesis of Loops, Functions, RAM, ROM, Shift register inference from arrays;

• Impact of Compiler Optimization in HLS results: Impact of Compiler optimizations like copy propagation, constant propagation, common sub-expression elimination, loop transformations, code motions, etc., in HLS results;

• Secure HLS, Relative Scheduling, IO scheduling modes, Pipelining, Handshaking, System Design, High-Level Synthesis for FPGA;

• RTL Optimizations Techniques: Various optimization techniques to improve latency, area and power in C-based VLSI designs;

• High-level Synthesis Verification: Simulation based verification, Translation validation. Equivalence checking between C and RTL;

Text Book:

• [Micheli] G. De Micheli. Synthesis and optimization of digital circuits, McGraw Hill, India Edition, 2003.

• [Elliot] J. P. Elliot, Understanding Behavioural Synthesis: A Practical guide to High-level Synthesis, Springer, 2nd edition, 2000

• [Kilts] Steve Kilts, Advanced FPGA Design, Wiley, 2007.

• [Parhi] K. Parhi: VLSI Digital Signal Processing Systems: Design and Implementation, Jan 1999, Wiley.

• [Huth] M. Huth and M. Ryan, Logic in Computer Science: Modelling and Reasoning about Systems, 2nd Ed, Cambridge University Press, 2004.

References:

• [Gajski] D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992

• [BlueBook] Mike Fingeroff, High-Level Synthesis Blue Book, Mentor Graphics Corporation, 2010.

• Philippe Coussy and Adam Morawiec, High-level Synthesis from Algorithm to Digital Circuit, Springer, 2008

• David. C. Ku and G. De Micheli, High-level Syntehsis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.

• T. F. Melham, Higher Order Logic and Hardware Verification, Cambridge University Press, 1993.

TAs:

• Priyanka Panigrahi (priya176101006@iitg.ac.in))

• Rajesh Kumar Jha (rajes174101007@iitg.ac.in)

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