Jan 2017 Session: CAD for VLSI (CS526)
Announcements:
05/05/2017: Marks for Project 2 Presentation


01/05/2017: End Sem Paper Evaluation: I will show your end sem evaluated papers on 5th May from 4PM-5PM in CSE Seminar Room (Ground Floor). You need to present during that time to clear any doubt/mistake in evaluation of your answer scripts.
24/04/2017: Xerox of Physical Synthesis (from N. Sherwani's book) are kept in Core 1 Xerox center. Collect your copy
21/04/2017: Class Test 5 schedule: 27th April, 2017, Thursday,  9AM-10AM, Syllabus: Physical Synthesis
18/04/2017: End Sem Syllabus: Topic covered post mid-Sem: (from 6th March to 27th April)
18/04/2017: Project Presentation 2: Check the revised schedule (attn Group 1 and 6) 17/4/2017: Class test 4 Marks
13/04/2017: Project Presentation 2: Check the revised schedule.
10/04/2017: No Class on Tuesday (11/04/2017). The class is rescheduled to Thursday (13/04/2017) 8-9AM slot. 31/03/2017: No Class on 3rd April 2017 (Monday). Next class will be on Tuesday (4th April 2017)
 27/03/2017: Warning to Non-performing students: I want to make it clear that the qualifying marks would be 40% in this course. So far, TEN students are below 40% till project 1 evaluation (out of 47.5). You HAVE to score 40% to pass. I will not entertain any request post EndSem to qualify you. Be prepare accordingly!
27/03/2017: Check my feedback on presentation 1
27/03/2017: TA will distribute Class Test 3 copies after tomorrow's class (28/03/2017) at 12PM. Clarifies your doubts on evaluation with TAs.
27/03/2017: Class Test 3 and Project Presentation Marks
08/03/2017: Mid Semester Evaluation: I will return your mid-sem answer scripts @9th March (Thursday), 2017, CSE Seminar Room, Ground Floor from     12:30PM to 1:30PM. You need to present during that time to clear any doubt/mistake in evaluation of your answer scripts.
08/03/2017: Revised Project Presentation Schedule. Check here
06/03/2017: Project Presentation Schedule is announced. Check here.
06/03/2017: Attendance till Mid-Semester
24/02/2017: Marks of Class Test 2
16/02/2017: Project Allocations
15/02/2017: Marks of Class Test 1
07/02/2017: There will be no class on next Friday (10/02/2017) and Monday ((13/02/2017) since I will out of station for an institute duty. These two classes are rescheduled to 15/02/2017 (Wednesday) and 22/02/2017 (Wednesday) from 6PM to 7PM.
 01/02/2017: Project/Research Study Groups Link Verify the data. Let me know if you find something wrong.

TAs:
Rajesh: d.rajesh@iitg.ernet.in
Piyoosh: piyoosh@iitg.ernet.in

Course plans and syllabus:
Marks distribution:
Quizzes: 20
Project: 15
MidSem: 25
End Sem: 40

Syllabus:
Introduction to CAD for VLSI
Brief introduction of hardware description language (Verilog),
Synthesis:
High-level Synthesis: Scheduling, Allocation and Binding,
Logic Synthesis: technology mapping, ASIC design methodology, FPGA based system design and prototyping,
Physical Design: Placements, routing algorithms,
Graph algorithms and their application in IC design;
Verification:
Binary Decision Diagram, Model Checking, Equivalence Checking Test,
Introduction to Digital Testing

Class Timmings :
Monday: 10AM-10:55AM
Tuesday: 11AM-11:55AM
Friday: 9AM-9:55AM

Reference Books:
1. G. De Micheli. Synthesis and optimization of digital circuits, 1st edition, 1994.
2. N. A. Sherwani, Algorithms for VLSI Physical Design Automation, Bsp Books Pvt. Ltd., 3rd edition, 2005.
3. D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992.
4. Huth and Ryan, "Logic for Computer Science"
5. S. H. Gerez, Algorithms for VLSI Design Automation.

Get a copy of De Micheli's book. For other book, I will provide xerox.


Sr. No Date Topic Covered Resource
1 09/01/2017 Introduction to CAD fo VLSI, course outline. Follow class notes
2 10/01/2017 High-level Synthesis (HLS): working with an example. Similar lecture by me
3 16/01/2017 HLS: Preprocessing, Behavioural optimizations Section 3.4 of De Micheli's book
4 17/01/2017 HLS: Scheduling problem formulation, ASAP, ALAP. Link to Prof. Balachandrans's slides on HLS
5 20/01/2017 HLS: Scheduling - ILP formulation Chapter 5 of De Micheli's book
6 23/01/2017 HLS: Scheduling - ILP formulation of Multiprocessor scheduling Chapter 5 of De Micheli's book
7 27/01/2017 HLS: Scheduling - HU's Algorithm, List Scheduling of ML-RC Chapter 5 of De Micheli's book
8 30/01/2017 HLS: Scheduling - List Scheduling for MR-LC, Force Directed Scheduling Chapter 5 of De Micheli's book
9 02/02/2017 HLS: Scheduling - GA Based scheduling Paper
10 06/02/2017 Verilog Tutorial Slides
11 07/02/2017 Verilog Tutorial, Class Test 1 Slides, Class Test 1 Question
12 14/02/2017 HLS: FU allocation  and Binding Chapter 6 of De Micheli's book
13 15/02/2017 HLS: Register Allocation and Binding Chapter 6 of De Micheli's book
14 17/02/2017 HLS: Port Assignments Problem Class Notes and Chapter 6 of De Micheli's book
15 20/02/2017 HLS: Datapath and controller Generation, Class Test 2 Class Notes, Class Test 2 Question
16 21/02/2017 RTL Optimizations: Retiming for Clock period minimization Paper1
17 22/02/2017 RTL Optimizations: Retiming for area minimization, Register Balancing Paper
18 22/02/2017 RTL Optimizations: Folding, Pipelining, Replication Scanned copy of Parhi's book, Scanned copy of Gajski's book, Replication paper
19 06/03/2017 Logic Synthesis: 2-level Logic optimization, Exact Logic Minimization Chapter 7 of De Micheli's book. ppt1, ppt2
20 07/03/2017 Logic Synthesis: ESPRESSO Chapter 7 of De Micheli's book. Notes
21 10/03/2017 Binary Decision Diagrams (BDD) Section 2.5 in De Micheli's book, ppt
22 14/03/2017 Multi-level Logic Synthesis - Heuristic based approach Chapter 8 of De Micheli's book. Sections 8.1 and 8.2
23 15/03/2017 Multi-level Logic Synthesis - Algebraic Approach Chapter 8 of De Micheli's book. Section 8.3, Notes
24 20/03/2017 Technology Mapping: FPGA Memory and DSP inference, ClassTest 3 Class Test 3
25 21/03/2017 Technology Mapping: FPGA LUT Mapping Paper
26 24/03/2017 Technology Mapping: Cut selection, ASIC Mapping Slide, Scribe for 24, 25 and 26
27 27/03/2017 Verification: Basics Slide
28 28/03/2017 HLS Verification: Scheduling Verification Slide, Paper
29 31/03/2017 HLS Verification: Alloc and Bind, CP-DP Verification Paper
30 04/04/2017 Combinational Circuit Verification, Class Test 4 Class test 4
31 07/04/2017 Combinational Circuit Verification Paper
32 10/04/2017 Sequential Circuit Verification slides
33 13/04/2017 Model Checking Basic slides, slides2
34 17/04/2017 Sequential Circuit Verification using model checking Paper
35 18/04/2017 Physical Synthesis Introduction, Partitioning: KL and FM algorithms Slide1, slide2, FM example, slide3
36 21/04/2017 Physical Synthesis: Floor Planning Slide
37 24/04/2017 Physical Synthesis: Placements Slide
38 25/04/2017 Physical Synthesis: Routing Slide 1, slide 2
39 27/04/2017 Routing, Class Test 5 Class Test 5, Slide


2016-2017, Even Semester, CS201 : Data Structure
 

2016-2017, Even Semester, CS210 : Data Structure Laboratory