MTech in Electronics and Electrical Engineering
(Specialization:
VLSI)
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Semester
I |
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Semester
II |
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Course
No |
Course
Name |
L-T-P-C |
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Course
No |
Course
Name |
L-T-P-C |
EC
502 |
Digital IC Design |
3-0-0-6 |
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EC
503 |
Analog IC Design |
3-0-0-6 |
EC
510 |
Semiconductor Device
Modeling and Technology |
3-0-0-6 |
|
EC
561 |
VLSI System Design |
3-0-0-6 |
EC
560 |
VLSI System for
Communications and Signal Processing |
3-0-0-6 |
|
EC
6xx |
Dept. Elective – III |
3-0-0/2-6/8 |
EC
6xx |
Dept. Elective – II |
3-0-0/2-6/8 |
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EC
513 |
VLSI Lab II |
0-0-3-3 |
EC
512 |
VLSI Lab I |
0-0-3-3 |
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EC
514 |
VLSI Lab III |
0-0-3-3 |
|
|
EC
697 |
Project Phase – I |
0-0-6-6 |
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Total |
12-0-3/5-27/29 |
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Total |
9-0-12/14-30/32 |
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Semester
III |
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Semester
IV |
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EC
698 |
Project Phase – II |
0-0-24-24 |
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EC
699 |
Project Phase - III |
0-0-24-24 |
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Total |
0-0-24-24 |
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|
Total |
0-0-24-24 |
EC 502 Digital Integrated Circuit Design (3-0-0-6)
Basic Electrical Properties of MOS circuits: MOS transistor operation in linear and saturated regions, MOS transistor threshold voltage, MOS switch and inverter, latch-up in CMOS inverter; sheet resistance and area capacitances of layers, wiring capacitances; CMOS inverter properties - robustness, dynamic performance, regenerative property, inverter delay times, switching power dissipation, MOSFET scaling - constant-voltage and constant-field scaling; dynamic CMOS design: steady-state behavior of dynamic gate circuits, noise considerations in dynamic design, charge sharing, cascading dynamic gates, domino logic, np-CMOS logic, problems in single- phase clocking, two-phase non-overlapping clocking scheme; subsystem design: design of arithmetic building blocks like adders – static, dynamic, Manchester carry-chain, look-ahead, linear and square-root carry-select, carry bypass and pipelined adders and multipliers - serial-parallel, Braun, Baugh-Wooley and systolic array multipliers, barrel and logarithmic shifters, area-time tradeoff, power consumption issues; designing semiconductor memory and array structures: memory core and memory peripheral circuitry.
Texts:
1. J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits- A Design Perspective, 2nd ed., PHI, 2003 2. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design - a System Perspective, 2nd ed., Pearson Education Asia, 2002
References:
1. S.M. Kang and Y. Leblevici, CMOS Digital Integrated Circuits Analysis and Design, 3rd ed., McGraw Hill, 2003 2. J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons (Asia) Pte Ltd, 2002 3. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1997 EC 503 Analog IC Design (3-0-0-6)
Introduction to analog VLSI and mixed signal issues in CMOS technologies; Basic MOS models, SPICE Models and frequency dependent parameters; Basic MNOS/CMOS gain stage, cascade and cascode circuits; Frequency response, stabilty and noise issues in amplifiers; CMOS analog blocks: Current Sources and Voltage references; Differential amplifier and OPAMP design; Frequency Synthesizers and Phased lock-loops; Non-linear analog blocks: comparators, charge-pump circuits and multipliers; Basics of data converters; Analog Testing and Layout issues; Low Voltage and Low Power Circuits; Introduction to RF Electronics.
Texts:
1. B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw Hill 2001 2. P. E. Allen and D. R. Holberg,
CMOS Analog Circuit Design, 2nd
edition, Oxford University Press, 1997
References:
1. B. Razavi, RF Microelectronics, Prentice-Hall,
1998. 2. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1997 3. P. R. Gray and R. G. Meyer, Analysis and design of Analog Integrated circuits 4th Edition, Wiley Student Edition, 2001. 4. D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley Student Edition, 2002.
EC 510 Semiconductor Device Modelling and Technology (3-0-0-6)
p-n Junctions: fabrication of p-n junctions, equilibrium conditions, forward and reverse-biased junctions, reverse-bias breakdown, transient and a-c conditions. Metal-semiconductor junctions: Schottky barriers, rectifying and ohmic contacts. Bipolar junction transistors: minority carrier distribution and terminal currents, generalized biasing, switching, secondary effects, frequency limitations of transistors. Field-Effect Transistors: JFET- current-voltage characteristics, effects in real devices, high-frequency and high-speed issues; MOSFET- basic operation and fabrication; ideal MOS capacitor; effects of real surfaces; threshold voltages; output and transfer characteristics of MOSFET. SPICE Models for Semiconductor Devices: MOSFET Level 1, Level 2 and level 3 model, Model parameters; SPICE models of p-n diode and BJT. Issues of digital IC design: general overview of design hierarchy, integration density and Moore’s law, MOSFET scaling. VLSI Fabrication principles crystal growth and doping, diffusion, epitaxy, ion implantation, film deposition, lithography, etching. MOSFET fabrication: basic steps of fabrication, CMOS p-well and n-well processes, layout design rules, Bi-CMOS fabrication process; basic electrical properties of MOS and Bi-CMOS circuits: MOS transistor operation in linear and saturated regions, MOS transistor threshold voltage, MOS switch and inverter, Bi-CMOS inverter, latch-up in CMOS inverter.
Texts:
1. N. DasGupta and A. DasGupta, Semiconductor Devices: Modelling and Technology, Prentice Hall of India Private Limited, New Delhi, 2004 2. J. D. Plummer, M.D. Deal and P.B. Griffin, Silicon VLSI Technology, Fundamentals, Practice and Modeling, Pearson education, 2000
References:
1. Y. Taur, and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University press, 1998 2. S. M. Sze, VLSI Technology, 2nd edition, McGraw-Hill, 1998 3. B. G. Streetman and S. Banerjee, Solid State Electronic Devices, 5th edition, Prentice Hall of India Private Limited, New Delhi, 2000.
EC 512 VLSI Laboratory-1 (0-0-3-3)
Prerequisite: Concurrently with EC 502 and EC510
Experiments are based on the following topics and will cover other areas when required Model Parameter extraction for a diode and MOSFET; NMOS and PMOS characteristics; Inverter characteristics; layout of resistors, capacitors, transistors and inverter; 1-bit Shift Register; digital logic cells; adders; multipliers; Ring Oscillator
Texts/References:
1. Muhammad H. Rashid, Introduction to PSpice Using OrCAD for Circuits and Electronics, 3rd
edition, Prentice-Hall India, 2006 2. Charles H Roth Jr., Digital Systems Design Using VHDL, 8th Indian reprint,
Thomson Learning Inc., 2006 3. J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital
Integrated Circuits- A Design Perspective, 2nd ed., PHI, 2003 4. N. H. E. Weste and K. Eshraghian, Principles
of CMOS
VLSI Design: A Systems Perspective, Pearson Education, 2004. 5. Mentor Graphics CAD software manuals.
EC 513 VLSI Laboratory-2 (0-0-3-3)
Prerequisite: Concurrently with EC 503
Experiments are based on the following topics and will cover other areas when required NMOS and PMOS characteristics; Common source amplifiers; Layout of resistors, capacitors, transistors; differential amplifier; cascode amplifier; current mirror; push pull CS amplifier; negative feedback amplifier; multistage amplifiers; operational amplifiers and comparators
Texts/References:
1. Muhammad H. Rashid, Introduction to PSpice Using OrCAD for Circuits and Electronics, 3rd
edition, Prentice-Hall India, 2006 2. B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw Hill 2001 3. B. Razavi, RF Microelectronics, Prentice-Hall,
1998. 4. P. E. Allen and D. R. Holberg,
CMOS Analog Circuit Design, 2nd
edition, Oxford University Press, 1997 5. D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley Student Edition, 2002. 6. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition,
Wiley Student Edition, 2001. 7. Mentor Graphics CAD software manuals
EC 514 VLSI Laboratory-3 (0-0-3-3)
Prerequisite: EC 560
Experiments/Projects are based on the following topics and will cover other areas when required RF front-end: LNA, Mixer, VCO, Frequency Synthesizer, Power Amplifiers and Filters; ADCs, DACs and Digital Compensation techniques; base band designs: Filters, FFT, DCT, Channel coders and Decoders - Viterbi, Reed Solomon, Turbo Codes; Modulation, Synchronization and Timing Recovery Circuits; Image/Video compression techniques.
Texts/References:
1. B. Razavi, RF Microelectronics, Prentice-Hall,
1998. 2. P. E. Allen and D. R. Holberg,
CMOS Analog Circuit Design, 2nd
edition, Oxford University Press, 1997 3. B. Leung, VLSI
for Wireless Communication, Person Education, 2002. 4. R.J. Plassche, CMOS Integrated Analog-to-Digital and
Digital-to-Analog Converters, John Wiley & Sons, Inc., 2004. 5. F. Horlin and A. Bourdoux, Digital
Compensation for Analog Front-Ends: A New Approach to Wireless Transceiver
Design, John Wiley & Sons, Inc., 2008 6. K. K. Parhi, VLSI Digital Signal Processing Systems,
Design and Implementation, Wiley Interscience,
2007 7. E. C. Ifeachor and B. W.
Jervis, Digital Signal Processing
– A Practical Approach, Second Edition, Pearson Education, 2002. 8. B. Sklar, Digital Communications, Pearson
Education, 2001 9.
Mentor Graphics
CAD software manuals.
EC 560 VLSI Systems for Communications and Signal Processing (3-0-0-6)
Generic transceiver architectures in current wireless communications systems: various wireless LAN standards and digital broadcast standards - DVB-T/S; Analog RF front-end modules of a communication receiver: LNA, filter, RF VGA, Mixer, IF Amplifier, VCO, Oscillators and Frequency Synthesizer; Digital IF Extension and AGC: ADCs and DACs at IF-level and AGC; Digital Baseband Modules: OFDM signal processing – Timing and Frequency Synchronization, FFT/IFFT, Adaptive Equalizer, Mapper/Demapper, Channel Encoder/Decoders, Viterbi, Reed-Solomon, Turbo Codes; Non-idealities in RF front-end: Non-linearities, Imperfect gain, DC- offset, Oscillator phase noise, I/Q mismatch. Digital Compensation techniques for front-end imperfections; Power Amplifier design issues in OFDM transmitter; Image/Video compression: core/compute-intensive algorithms – DCT/IDCT, motion estimation and compensation; candidate VLSI structures.
Texts/ References:
1. B. Leung, VLSI
for Wireless Communication, Person Education, 2002. 2. B. Razavi, RF Microelectronics, Prentice-Hall,
1998. 3. R.J. Plassche, CMOS Integrated Analog-to-Digital and
Digital-to-Analog Converters, John Wiley & Sons, Inc., 2004. 4. F. Horlin and A. Bourdoux, Digital
Compensation for Analog Front-Ends: A New Approach to Wireless Transceiver
Design, John Wiley & Sons, Inc., 2008 5. K. K. Parhi, VLSI Digital Signal Processing Systems,
Design and Implementation, Wiley Interscience,
2007 6. J.E. France, Y. Tsividis,
Design of Analog-Digital VLSI Circuits
for Telecommunication and Signal Processing, Prentice Hall, 1994 7. E. C. Ifeachor and B. W.
Jervis, Digital Signal Processing
– A Practical Approach, Second Edition, Pearson Education, 2002. 8. B. Sklar, Digital Communications, Pearson
Education, 2001. EC 561 VLSI System Design (3-0-0-6)
Prerequisite: EC502 Digital IC Design
Basics of system hardware design: Hierarchical design using top-down and bottom-up methodology, System partitioning techniques, interfacing between system components, Handling multiple clock domains, Synchronous and asynchronous design styles; Design of finite state machines: state assignment strategies; The Processor: Data path and Control, Enhancing performance with Pipelining, exploiting of Memory hierarchy.
Texts/ References:
1. G. De. Micheli, Synthesis and Optimisation
of Digital Circuits, Tata McGraw-Hill, 2004. 2. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The
Hardware/Software Interface, 2nd Edition, Morgan Kaufmann Publishers,
Inc, 1998. 3. J. Rabaey, Digital Integrated Circuits, A Design Perspective, 2nd Edition, Pearson Education,
2003. 4. H. E. Weste and K. Eshraghian, Principles
of CMOS VLSI Design, 2nd
Edition, Eight Indian Reprint, Pearson Education, 2002. 5. C. Mead and L. Conway, Introduction to VLSI Systems, Addison Wesley, 1979. . |
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